• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.85-89
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• 2022

We reported on annealing effect on Ga₂O₃/Al₂O₃/SiC devices grown by radio frequency sputtering method. Post-deposition annealing at 900 ℃ was performed, which results in crystallization in the Ga₂O₃ films. The major peaks (-401) and (403) of Ga₂O₃ which was thermally treated at 900 ℃ appears in the x-ray diffraction (XRD) results. Auger electron spectroscopy (AES) shows that Ga and Al atoms seems to be diffused into the opposite direction Al₂O₃ and Ga₂O₃ after annealing. Transfer and output characteristics of back-gate transistor were analyzed where SiC substrate is used as gate material. On-state current and on/off ratio increased almost 10⁹ and 10⁶ times higher in the 900 ℃ annealed sample.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1182-1184
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• 2006

A mica has been introduced as a new substrate material for the fabrication of the poly-Si TFTs. A poly-Si film is produced on the mica substrate at $550^{\circ}C$ by the nickel-induced crystallization and the poly-Si TFTs on the mica substrate are successfully fabricated for the first time.

• Journal of Information Display
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• v.4 no.3
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• pp.17-21
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• 2003

A low temperature doping technique to be applied in poly-Si TFTs on plastic substrates was investigated. Heavily-doped amorphous silicon layers were deposited on poly-Si and the dopant atoms were driven in by subsequent excimer laser annealing. The entire process was carried out under a substrate temperature of 120 $^{\circ}C$, and a sheet resistance of as low as 300 ${\Omega}$/sq. was obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Vacuum Magazine
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• v.3 no.3
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• pp.15-18
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• 2016

In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.274-277
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• 2000

Thin Film Transistor(TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature(500$^{\circ}C$) Metal-Induced Lateral Crystallization(MILC) furnace annealing and high -temperature (700$^{\circ}C$) rapid thermal annealing leads to the improvement of the material quality The TFTs measured with this two-step annealing material exhibit better characteristics than those obtained by using conventional MILC furnace annealing.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.339-343
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• 1999

This paper reports the characteristics of poly-Si TFT unitary CMOS circuits fabricated with various techniques, in order to investigate the optimum process conditions. The active films were deposited by PECVD and LPCVD using $SiH_4\; and\; Si_2H_6$ as source gas, and annealed by SPC and ELA methods. The impurity doping of the oource and drain electrodes was performed by ion implantation and ion shower. In order to investigate the AC characteristics of the poly-Si TFTs processed with various methods, we have examined the current driving characteristics of the polt-Si TFT and the frequency characteristics of 23-stage CMOS ring oscillators. Ithas been observed that the circuits fabricated using $Si_2H_6$ with low-temperature process of ELA exhibit high switching speed and current driving performances, thus suitable for real application of large area electronics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.217-221
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• 2004

[ $CO_2$ ]laser ablation rates for bulk 4H-SiC substrates and GaN/AIN/SiC templates in the range 229-870 ${\mu}m.min^{-1}$ were obtained for pulse energies of 7.5-30 mJ over diameters of 50·500 ${\mu}m$ with a Q-switched pulse width of ${\sim}30$ nsec and a pulse frequency of 8 Hz. The laser drilling produces much higher etch rates than conventional dry plasma etching (0.2 - 1.3 ${\mu}m/min$) making this an attractive maskless option for creating through-wafer via holes in SiC or GaN/AlN/SiC templates for power metal-semiconductor field effect transistor applications. The via entry can be tapered to facilitate subsequent metallization by control of the laser power and the total residual surface contamination can be minimized in a similar fashion and with a high gas throughput to avoid redeposition. The sidewall roughness is also comparable or better than conventional via holes created by plasma etching.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.