• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.7
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• pp.670-674
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• 1991

This paper presents the material properties of LPCVD silicon films formed using Si2H6 gas at various deposition temperatures. To study the structural properties depending on the deposition temperature, XRD, EBD and TEM analyses were used. The maximum grain size in this experiment was obtained at the deposition temperature of 485ø C. It is discussed that LPCVD films formed below the deposition temperature of 485ø C are promising for low temperature TFT applications. The enhancement of the film characteristics results from the reduction of grain boundary density. We also observed that the film properties of Si2H6 at 600ø C was quite different from those of Si H4 at 600ø C. It has shown that the grain structure from a TEM analysis was elliptical and not dependent on the deposition temperature.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1998.09a
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• pp.35-40
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• 1998

There have two kinds of defects, planar defects and vertical defects which were called micropipes in SiC bulk crystals grown by a sublimation method. We could decrease these defects by adding a little piece of Si in the SiC powder or using Ta cylinder in the crucible. so were report the dependence of these defects in a wafer on silicon/carbon ratio in this paper. The chemical species sublimed from SiC powder is affected by carbon from the graphite wall of the crucible. It is important to control the chemical species on the substrate.

• Korean Journal of Materials Research
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• v.23 no.1
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.785-789
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• 2013

Silicon Carbide (SiC) is the material with the wide band-gap (3.26 eV), high critical electric field (~2.3 MV/cm), and high bulk electron mobility (~900 $cm^2/Vs$). These electronic properties allow attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. In general, device design has a significant effect on the switching and electrical characteristics. It is known that in this paper, we demonstrated that the switching performance and breakdown voltage of IGBT is dependent with doping concentration of p-base region and drift layer by using 2-D simulations. As a result, electrical characteristics of SiC-IGBT deivce is higher breakdown voltage ($V_B$= 1,600 V), lower on-resistance ($R_{on}$= 0.43 $m{\Omega}{\cdot}cm^2$) than Si-IGBT. Also, we determined that processing time and cost is reduced by the depth of n-drift region of IGBT was reduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.37-38
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.9
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• pp.737-740
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics, In this paper, we demonstrated that the switching performance of DMOSFETs are dependent on the with Channel length ($L_{channel}$) and Current Spreading Layer thickness ($T_{CSL}$) by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the JFET region, CSL, and epilayer. It is found that improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance. Therefore, accurate modeling of the operating conditions are essential for the optimizatin of superior switching performance.

• Journal of Powder Materials
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• v.18 no.6
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• pp.562-567
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• 2011

This paper reports the effect of sintering processes and additives on the microstructures and mechanical properties of $ZrB_2$-SiC composite ceramics. We fabricated sintered bodies of $ZrB_2$-20 vol.% SiC with or without sintering additive, such as C or $B_4C$, densified by spark plasma sintering as well as hot pressing. While almost full densification was achieved regardless of sintering processes or sintering additives, significant grain growth was observed in the case of spark plasma sintering, especially with $B_4C$. With sintered bodies, mechanical properties, such as flexural strength and Vickers hardness, were also examined.

• Journal of Power Electronics
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• v.12 no.1
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• pp.19-23
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• 2012

This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.

• 한국신재생에너지학회:학술대회논문집
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• 2005.06a
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• pp.113-116
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• 2005

In this paper, silicon thin-film solar cells(Si- TFSC) and a-Si/c-Si heterojunction solar cells(HJ-cell) are investigated. The Si-TFSC was prepared on glass substrate by depositing $1-3{\mu}m$ thin-film silicons by glow discharge method. The $a-Si:H/{\mu}c-Si:H$ tandem solar cells on textured ZnO:A1 TCO (transparent conducting oxide) showed improved Jsc in top and bottom cells than that on $SnO_2:F$ TCO. This enhancement of jsc resulted from improved light trapping effect by front textured ZnO:A1. The a-Si/c-Si HJ-cells with simple structure without high efficiency features are suffering from low Voc and Jsc. The improvement of front nip and back interface properties by adopting high quality silicon-films at low temperature should be done both for increasing device performances and production cost.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.