• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• 한국진공학회지
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• 제19권4호
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• pp.307-313
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• 2010

본 연구에서는 열 화학기상증착법(thermal chemical vapor deposition)을 이용하여 분말 형태의 규소(Si)와 염화니켈 수화물 $(NiCl_2{\cdot}6H_2O)$을 혼합한 후 탄소공급원인 $CH_4$ 가스를 주입하여 탄화규소 나노선(SiC nanowire)을 합성하였다. 합성 온도와 $CH_4$ 가스 유량 변화에 따른 탄화규소 나노선의 구조적 특성을 분석한 결과, 합성온도가 $1,400^{\circ}C$, $CH_4$ 가스의 유량이 300 sccm인 경우가 탄화규소 나노선의 합성에 최적화된 조건임을 라만 분광법(Raman spectroscopy)과 X-선 회절(X-ray diffraction), 주사전자현미경(scanning electron microscopy), 그리고 투과전자현미경(transmission electron microscopy) 분석을 통해 확인하였다. 합성된 탄화규소 나노선의 직경은 약 50~150 nm이며, 곧은 방향성과 높은 결정성을 가지는 입방구조(cubic structure)를 지니고 있었다.

• 한국재료학회지
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• 제18권10호
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• pp.529-534
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• 2008

The hydrogen gas sensing properties of a zinc oxide nanowire structure were studied. Porous zinc oxide nanowire structures were fabricated by oxidizing zinc deposited on a single-wall carbon nanotube (SWNT) template. This revealed a porous ZnO-SWNT composite due to the porosity in the SWNT film. The gas sensing properties were compared with those of zinc oxide thin films deposited on SiO2/Si substrates in sensitivity and operating temperature. The composite structure showed higher sensitivity and lower operating temperature than the zinc oxide film. It showed a response even at room temperature while the film structure did not.

• 한국진공학회지
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• 제22권2호
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• pp.105-110
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• 2013

Vapor-Liquid-Solid 방법을 이용하여 다양한 성장온도와 V/III 비율 아래 $In_xGa_{1-x}As$ 나노와이어를 실리콘 (111) 기판 위에 성장하였다. 나노와이어 성장은 화학기상증착(MOCVD)장치를 이용하였으며, 나노와이어의 구조적 특성은 주사전자현미경 및 투과전자현미경을 이용하여 분석하였다. 나노와이어의 조성비 분포를 확인하기 위하여 투과전자현미경에 장착된 Energy dispersive X-ray 분석기로 나노와이어의 길이에 따른 In과 Ga의 조성비를 측정하였다. 성장온도와 V/III 비율이 올라갈수록 In 조성비가 나노와이어 내부에서 크게 변하는 것을 확인하였는데, 이는 Vapor-Solid 방식에 의한 나노와이어 표면에서의 성장이 증가하기 때문으로 이해된다.

• 한국세라믹학회지
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• 제55권3호
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• pp.285-289
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• 2018

We synthesized silicon carbide (${\beta}-SiC$) nanowires with nano-scale diameter (30 - 400 nm) and micro-scale length ($50-200{\mu}m$) on a porous body using low-grade silica and carbon black powder by carbothermal reduction at $1300-1600^{\circ}C$. The SiC nanowires were formed by vapor-liquid-solid deposition with self-evaporated Fe catalysts in low-grade silica. We investigated the characteristics of the SiC nanowires, which were grown on a porous body with Ar flowing in a vacuum furnace. Their structural, optical, and electrical properties were analyzed with X-ray diffraction (XRD), transmission electron microscopy (TEM), and selective area electron diffraction (SAED). We obtained high-quality SiC single crystalline nanowire without stacking faults that may have uses in industrial applications.

• Bulletin of the Korean Chemical Society
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• 제34권11호
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• pp.3451-3455
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• 2013

Single-crystalline silicon nanowires (SiNWs) were fabricated by using an electroless metal-assisted etching of bulk silicon wafers with silver nanoparticles obtained by wet electroless deposition. The etching of SiNWs is based on sequential treatment in aqueous solutions of silver nitrate followed by hydrofluoric acid and hydrogen peroxide. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the Si substrate were produced. Free-standing SiNWs were then obtained using ultrasono-method in toluene. Alkyl-derivatized SiNWs were prepared to prevent the aggregation of SiNWs and obtained from the reaction of SiNWs and dodecene via hydrosilylation. Optical characterizations of SiNWs were achieved by FT-IR spectroscopy and indicated that the surface of SiNWs is terminated with hydrogen for fresh SiNWs and with dodecyl group for dodecyl-derivatized SiNWs, respectively. The main structures of dodecyl-derivatized SiNWs are wires and rods and their thicknesses of rods and wire are typically 150-250 and 10-20 nm, respectively. The morphology and chemical state of dodecyl-derivatized SiNWs are characterized by scanning electron microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.766-769
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• 2008

Zinc oxide (ZnO) nanowires were prepared on Si substrates by a thermal evaporation method at different temperatures and $O_2$ pressure. Microstructural analysis of the obtained ZnO nanowires was performed by using transmission electron microscopy(TEM) and scanning electron microscopy(SEM). Phase analysis was done using X-ray diffraction(XRD). As the deposition temperature and oxygen pressure were increased, the diameter and length of ZnO nanowires had a tendency to increase. Based on TEM and XRD analyses, the nanowires are single crystalline in nature and consist of a single phase. According to the measurements, the ZnO nanowires grown at 1100$^{\circ}C$, Ar 50 sccm, $O_2$ 10 sccm have good properties.

• EDISON SW 활용 경진대회 논문집
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• 제5회(2016년)
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.109-110
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• 2007

Pyrrole and DNA can be used for synthesis of conducting nanowires. Protonated pyrrole and negatively charged DNA are absorbed by electrostatic interaction. The level of absorbance is related to pH of pyrrole. Therefore, DNA immobilized and aligned on the 3-aminopropyltrimethoxysi1ane (APTES) modified Si surface. Positive pyrrole monomers was deposited on aligned DNA for the synthesis of nanowire in various pH condition. And polypyrrole nanowires were synthesized by polimerization with ammonium persulfate (APS). These polypyrrole nanowires were measured by AFM, and then we found optimal pH level for the synthesis of nanowires.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1548-1549
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• 2007

이 실험은 간단한 가열로(heating furnace)를 이용 thermal CVD(chemical Chemical Depositin) 방법을 사용하여, 촉매를 사용하지 않고 실리콘 나노와이어(Si nanowire)를 합성하는 방법에 대해서 연구한 것이다. 굴곡도(roughness)가 큰 알루미나(($Al_{2}O_{3}$) 기판을 사용하여 금(Au)과 같은 촉매를 사용하지 않고 실리콘 나노와이어를 성장시켜 대략 20nm 전후의 지름을 가진 실리콘 나노와이어를 성장시킬 수 있었다. 이 방법은 금을 촉매로 이용하는 방법에 비하여 기판위에 증착되어 성장된 실리콘 나노와이어가 직전성을 가지지 못하고 꼬여있어서 나노와 이어의 분산 과저에서 어려움이 존재하지만 촉매를 사용하지 않기 때문에 성장된 나노와이어에서 촉매를 제거해야하는 어려움을 생략할 수 있고, 기판 위에 촉매를 seeding 하는 작업을 거치지 않고도 20nm 정도의 실리콘 나노와이어를 성장시킬 수 있는 간단한 방법이다.