• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.7
• /
• pp.584-592
• /
• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.6
• /
• pp.491-495
• /
• 2007

This paper has demonstrated the electrical properties of SiGe pMOSFETs fabricated on both bulk-Si and PD SOI substrates. Two principal merits, the mobility increase in strained-SiGe channel and the parasitic capacitance reduction of SOI isolation, resulted in improvements in device performance. It was observed that the SiGe PD SOI could alleviate the floating body effect, and consequently DIBL was as low as 10 mV/V. The cut-off frequency of device fabricated on PD SOI substrate was roughly doubled in comparison with SiGe bulk: from 6.7 GHz to 11.3 GHz. These experimental result suggests that the SiGe PD SOI pMOSFET is a promising option to drive CMOS to enhance performance with its increased operation frequency for high speed and low noise applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.317-320
• /
• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.7
• /
• pp.1363-1374
• /
• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Proceeding of EDISON Challenge
• /
• 2017.03a
• /
• pp.372-375
• /
• 2017

Metal-oxide-semiconductor Field-Effect transistor (MOSFET)을 대체할 기술로서 제안된 Schottky Barrier MOSFET (SB-MOSFET)가 제시되고 있다. 본 연구에서는 SB-MOSFET와 MOSFET을 다양한 소자 파라미터를 변화시킴으로서 양자역학적 전하수송 계산을 바탕으로 특성을 분석한다. MOSFET과 SB-MOSFET은 채널 두께 ($T_{Si}$)가 감소함에 따라 전류량은 증가하고 SS와 DIBL은 증가하였고 Overlap에서는 SS와 DIBL이 커지고 Underlap에서는 작아짐을 보였고 SB-MOSFET는 특히 그 폭이 컸다. 또한 SB 높이가 낮을수록 SB-MOSFET의 전류량이 증가하고 SS는 감소하였고 마찬가지로 Source와 Drain doping concentration이 낮을수록 MOSFET의 전류량은 증가하고 SS는 감소하였다. MOSFET과 SB-MOSFET의 경향은 대체로 비슷하나 변화량의 차이 등이 있었다.

• Journal of Sensor Science and Technology
• /
• v.15 no.1
• /
• pp.1-6
• /
• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.1
• /
• pp.109-114
• /
• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Proceedings of the KIPE Conference
• /
• 2019.11a
• /
• pp.82-84
• /
• 2019

본 논문에서는 Induction Heating(IH) 시스템에서 WBG 소자인 SiC MOSFET과 GaN Transistor의 Performance 비교를 통해서 소자의 적합성을 분석한다. SiC 및 GaN 소자를 직렬 공진형 컨버터로 구성된 IH 시스템에 적용하여 온도, 전압, 전류, Gate 저항 등을 고려한 도통 손실, 스위칭 손실, 역방향 도통 손실과 열 해석 프로그램을 통한 열 성능 등의 비교가 수행되며, 이를 통해 소자 적합성이 분석된다. 각 소자에 따른 IH 시스템에 대한 시뮬레이션을 수행하여, 이론적 손실 비교를 통한 소자 적합성 분석에 대한 타당성을 검증한다.

• Ceramist
• /
• v.4 no.1
• /
• pp.46-55
• /
• 2001

$SiO_2$ 절연막의 우수한 절연특성 및 계면 특성으로 인해 지난 40여년 간 MOSFET 소자에 사용되어 왔으나, 차세대 $0.1{\mu}m$ 소자에서는 direct tunneling에 의한 누설전류가 지나치게 증가하여 더 이상 사용되기가 어렵다. 이에 대한 대안으로 많은 연구 그룹에서 고유전율 박막에 대한 연구를 하고 있으나 아직까지 $SiO_2$와 비교할 만한 탁월한 계면특성을 가진 절연막은 개발되어 있지 않아서, 수년 내에 개발될 $0.1{\mu}m$ MOSFET 소자의 개발에 가장 심각한 기술적 문제로 지적되고 있다. 현재의 연구경향을 종합할 때, $HfO_2$, $ZrO_2$, $HfSiO_x$, $ZrSiO_x$를 이용하여 계면 공정의 최적화를 통해 1-2nm급의 절연막을 구현하고, 1nm급 이하에서는 이보다 더 높은 유전상수를 가지는 재료의 선택과 이를 epitaxy로 성장시키는 방법에 대한 연구가 필수적이다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.5
• /
• pp.12-17
• /
• 2011

In this work, the analog performances of n-MOSFET fabricated on strained-Si/relaxed Si buffer layer with Ge mole fractions and thermal annealing temperatures after device fabrication have been characterized in Depth. The effective electron mobility was increased with the increase of Ge mole fraction for all annealing temperatures. However the effective electron mobility was decreased at the Ge mole fraction of 32%. The analog performances were enhanced with the increase of Ge mole fraction at the room temperature but they were degraded at the Ge mole fraction of 32%. Since the degradation of the effective electron mobility of strained-Si layer is more significant than one of conventional Si layer at elevated temperature, the degradation of analog performances of SGOI devices were increased than those of SOI devices.