• Journal of Sensor Science and Technology
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• v.10 no.5
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• pp.337-342
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• 2001

Infrared sensors with one or two dimensional arrays are usually bonded via indium bumps to Si CMOS read out circuits. Therefore, both sensing of infrared beams and processing of signals are performed at the focal plane. This gives us a benefit of reducing noise as well as size of infrared detectors. We have developed a way of boding indium bumps with keeping sensor and ROIC parallel to each other. The flip chip bonder developed has a very simple structure and is easy to operate. So we expect that reliability will be improved very much.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.887-890
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• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1033-1036
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• 2003

In this paper, Si anisotropic etching characteristics of tetramethylammonium hydroxide (TMAH)/ ammonium persulfate (AP) solutions were investigated to realize the optimum structure of a diaphragm for the piezoresistive pressure sensor application. Due to its low toxicity and its high compatibility with the CMOS processing, TMAH was used as Si anisotropic etchants. The variations of Si etch rate on the etching temperature, TMAH concentration, and etching time were obtained. With increasing the etching temperature and decreasing TMAH concentrations, the Si etch rate is increased while a significant non-uniformity exists on the etched surface because of formation of hillocks on the <100> surface. With the addition of AP to TMAH solution, the Si etch rate is increased and an improvement in flatness on the etching front is observed. The Si etch rate is also maximized with increasing the number of addition of AP to TMAH solution per one hour. The Si square diaphragms of 20${\mu}{\textrm}{m}$ thickness and 100~400${\mu}{\textrm}{m}$ one-side length were fabricated successfully by applying optimum Si etching conditions of TMAH/AP solutions.

• Journal of IKEEE
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• v.27 no.4
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• pp.386-390
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• 2023

In this study, we examined the quasi-nonvolatile memory characteristics of silicon nanosheet (SiNS) feedback field-effect transistors (FBFETs) fabricated using a complementary metal-oxide-semiconductor process. The SiNS channel layers fabricated by photoresist overexposure method had a width of approximately 180 nm and a height of 70 nm. The SiNS FBFETs operated in a positive feedback loop mechanism and exhibited an extremely low subthreshold swing of 1.1 mV/dec and a high ON/OFF current ratio of 2.4×10⁷. Moreover, SiNS FBFETs represented long retention time of 50 seconds, indicating the quasi-nonvolatile memory characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.385-385
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• 2012

A two terminal N+/P/N+ junction device to replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque (STT) MRAM based on 3D device simulation. An N+/P/N+ junction structure with $30{\times}30nm$ area requires bi-directional current flow enough to write a data by a drain induced barrier lowering (DIBL) under a reverse bias at N+/P (or P/N+ junction), and high current on/off ratio of 106. The SiGe materials are widely used in hetero-junction bipolar transistors, bipolar compensation metal-oxide semiconductors (BiCMOS) since the band gap of SiGe materials can be controlled by changing the fraction and the strain epilayers, and the drift mobility is increased with the increasing Ge content. In this work, N+/P/N+ SiGe material based junction provides that drive current is increased from 40 to $130{\mu}A$ by increased Ge content from 10~80%. When Ge content is about 20%, the drive current density of SiGe device substantially increased to 2~3 times better than Si-based junction device in case of 28 nm P length, which is sufficient current to operation of STT-MRAM.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.19-22
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• 2003

In this paper, Si anisotropic etching characteristics of tetramethylammonium hydroxide (TMAH)/ammonium persulfate (AP) solutions were investigated to realize the optimum structure of a diaphragm for the piezoresistive pressure sensor application. Due to its low toxicity and its high compatibility with the CMOS processing, TMAH was used as Si anisotropic etchants. The variations of Si etch rate on the etching temperature, TMAH concentration, and etching time were obtained. With increasing the etching temperature and decreasing TMAH concentrations, the Si etch rate is increased while a significant non-uniformity exists on the etched surface because of formation of hillocks on the <100> surface. With the addition of AP to TMAH solution, the Si etch rate is increased and an improvement in flatness on the etching front is observed. The Si etch rate is also maximized with increasing the number of addition of AP to TMAH solution per one hour. The Si square diaphragms of 20$\mu\textrm{m}$ thickness and 100-400 $\mu\textrm{m}$ one-side length were fabricated successfully by adding AP of (5/6)g to 800 ml TMAH solution every 10 minutes.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.8-16
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• 2017

In this paper, we review studies attempting to triumph over the limitation of Si-based semiconductor technologies through a heterogeneous integration of high mobility compound semiconductors on a Si substrate, and the co-integration of electronic and/or optical devices. Many studies have been conducted on the heterogeneous integration of various materials to overcome the Si semiconductor performance and obtain multi-purpose functional devices. On the other hand, many research groups have invented device fusion technologies of electrical and optical devices on a Si substrate. They have co-integrated Si-based CMOS and InGaAs-based optical devices, and Ge-based electrical and optical devices. In addition, chip and wafer bonding techniques through TSV and TOV have been introduced for the co-integration of electrical and optical devices. Such intensive studies will continue to overcome the device-scaling limitation and short-channel effects of a MOS transistor that Si devices have faced using a heterogeneous integration of Si and a high mobility compound semiconductor on the same chip and/or wafer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.456-456
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• 2010

CMOS 소자가 서브마이크론($0.1\;{\mu}m$) 이하로 스케일다운 되면서 단채널 효과(short channel effect), 게이트 산화막(gate oxide)의 누설전류(leakage current)의 증가와 높은 직렬저항(series resistance) 등의 문제가 발생한다. CMOS 소자의 구동전류(drive current)를 높이고, 단채널 효과를 줄이기 위한 가장 효율적인 방법은 소스 및 드레인의 얕은 접합(shallow junction) 형성과 직렬 저항을 줄이는 것이다. 플라즈마 도핑 방법은 플라즈마 밀도 컨트롤, 주입 바이어스 전압 조절 등을 통해 저 에너지 이온주입법보다 기판 손상 및 표면 결함의 생성을 억제하면서 고농도로 얕은 접합을 형성할 수 있다. 그리고 얕은 접합을 형성하기 위해 주입된 불순물의 활성화와 확산을 위해 후속 열처리 공정은 높은 온도에서 짧은 시간 열처리하여 불순물 물질의 활성화를 높여주면서 열처리로 인한 접합 깊이를 얕게 해야 한다. 그러나 접합의 깊이가 줄어듦에 따라서 소스 및 드레인의 표면 저항(sheet resistance)과 접촉저항(contact resistance)이 급격하게 증가하는 문제점이 있다. 이러한 표면저항과 접촉저항을 줄이기 위한 방안으로 실리사이드 박막(silicide thin film)을 형성하는 방법이 사용되고 있다. 본 논문에서는 (100) p-type 웨이퍼 He(90 %) 가스로 희석된 $PH_3$(10 %) 가스를 사용하여 플라즈마 도핑을 실시하였다. 10 mTorr의 압력에서 200 W RF 파워를 인가하여 플라즈마를 생성하였고 도핑은 바이어스 전압 -1 kV에서 60 초 동안 실시하였다. 얕은 접합을 형성하기 위한 불순물의 활성화는 ArF(193 nm) excimer laser를 통해 $460\;mJ/cm^2$의 에니지로 열처리를 실시하였다. 그리고 낮은 접촉비저항과 표면저항을 얻기 위해 metal sputter를 통해 TiN/Ti를 $800/400\;{\AA}$ 증착하고 metal RTP를 사용하여 실리사이드 형성 온도를 $650{\sim}800^{\circ}C$까지 60 초 동안 열처리를 실시하여 $TiSi_2$ 박막을 형성하였다. 그리고 $TiSi_2$의 두께를 측정하기 위해 TEM(Transmission Electron Microscopy)을 측정하였다. 화학적 결합상태를 분석하기 위해 XPS(X-ray photoelectronic)와 XRD(X-ray diffraction)를 측정하였다. 접촉비저항, 접촉저항과 표면저항을 분석하기 위해 TLM(Transfer Length Method) 패턴을 제작하여 I-V 특성을 측정하였다. TEM 측정결과 $TiSi_2$의 두께는 약 $580{\AA}$ 정도이고 morphology는 안정적이고 실리사이드 집괴 현상은 발견되지 않았다. XPS와 XRD 분석결과 실리사이드 형성 온도가 $700^{\circ}C$에서 C54 형태의 $TiSi_2$ 박막이 형성되었고 가장 낮은 접촉비저항과 접촉저항 값을 가진다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.503-504
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• 2006

This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.209-213
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• 2010

This paper describes the fabrication and characteristics of AlN piezoelectric MPG(micro power generator). The micro energy harvester was fabricated to convert ambient vibration energy to electrical power as a AlN piezoelectric cantilever with Si proof-mass. To be compatible with CMOS process, AlN thin film was grown at low temperature by RF magnetron sputtering and micro power generators were fabricated by MEMS technologies. X-ray diffraction pattern proved that the grown AlN film had highly(002) orientation with low value of FWHM(full width at the half maximum, $\theta=0.276^{\circ}$) in the rocking curve around(002) reflections. The implemented harvester showed the $198.5\;{\mu}m$ highest membrane displacement and generated 6.4 nW of electrical power to $80\;k{\Omega}$ resistive load with $22.6\;mV_{rms}$ voltage from 1.0 G acceleration at its resonant frequency of 389 Hz. From these results, the AlN piezoelectric MPG will be possible to suitable with the batch process and confirm the possibility for power supply in portable, mobile and wearable microsystems.