• 한국정보통신학회논문지
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• 제18권9호
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• pp.2183-2188
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 채널 도핑농도 변화에 따른 문턱전압이동 현상에 대하여 분석하였다. 비대칭 DGMOSFET는 일반적으로 저 농도로 채널을 도핑하여 완전결핍상태로 동작하도록 제작한다. 불순물산란의 감소에 의한 고속 동작이 가능하므로 고주파소자에 응용할 수 있다는 장점이 있다. 미세소자에서 필연적으로 발생하고 있는 단채널 효과 중 문턱전압이동현상이 비대칭 DGMOSFET의 채널도핑농도의 변화에 따라 관찰하고자 한다. 문턱전압을 구하기 위하여 해석학적 전위분포를 포아송방정식으로부터 급수형태로 유도하였다. 채널길이와 두께, 산화막 두께 및 도핑분포함수의 변화 등을 파라미터로 하여 도핑농도에 따라 문턱전압의 이동현상을 관찰하였다. 결과적으로 도핑농도가 증가하면 문턱전압이 증가하였으며 채널길이가 감소하면 문턱전압이 크게 감소하였다. 또한 채널두께와 하단게이트 전압이 감소하면 문턱전압이 크게 증가하는 것을 알 수 있었다. 마지막으로 산화막 두께가 감소하면 문턱전압이 증가하는 것을 알 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 춘계학술대회
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• pp.748-751
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• 2014

본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 채널 도핑농도 변화에 따른 문턱전압이동현상에 대하여 분석하였다. 비대칭 DGMOSFET는 일반적으로 저농도로 채널을 도핑하여 완전결핍상태로 동작하도록 제작한다. 불순물산란의 감소에 의한 고속동작이 가능하므로 고주파소자에 응용할 수 있다는 장점이 있다. 미세소자에서 필연적으로 발생하고 있는 단채널효과 중 문턱전압이동현상이 비대칭 DGMOSFET의 채널도핑농도의 변화에 따라 관찰하고자 한다. 문턱전압을 구하기 위하여 해석학적 전위분포를 포아송방정식으로부터 급수형태로 유도하였다. 채널길이와 두께, 산화막두께 및 도핑분포함수의 변화 등을 파라미터로 하여 도핑농도에 따라 문턱전압의 이동현상을 관찰하였다. 결과적으로 도핑농도가 증가하면 문턱전압이 증가하였으며 채널길이가 감소하면 문턱전압이 크게 감소하였다. 또한 채널두께와 하단게이트 전압이 감소하면 문턱전압이 크게 증가하는 것을 알 수 있었다. 마지막으로 산화막두께가 감소하면 문턱전압이 증가하는 것을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권3호
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Biomolecules & Therapeutics
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• 제18권4호
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• pp.448-453
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• 2010

Drug-induced long QT syndrome is known to be associated with the onset of torsades de pointes (TdP), resulting in a fatal ventricular arrhythmia. QT interval prolongation can result from blocking the human ether-a-go-go-related gene (hERG) channel, which is important for the repolarization of cardiac action potential. Nicardipine, a Ca-channel blocker and antihypertensive agent, has been reported to increase the risk of occasional serious ventricular arrhythmias. We studied the effects of nicardipine on hERG $K^+$ channels expressed in HEK293 cells and Xenopus oocytes. The cardiac electrophysiological effect of nicardipine was also investigated in this study. Our results revealed that nicardipine dose-dependently decreased the tail current of the hERG channel expressed in HEK293 cells with an $IC_{50}$ of 0.43 ${\mu}M$. On the other hand, nicardipine did not affect hERG channel trafficking. Taken together, nicardipine inhibits the hERG channel by the mechanism of short-term channel blocking. Two S6 domain mutations, Y652A and F656A, partially attenuated (Y652A) or abolished (F656A) the hERG current blockade, suggesting that nicardipine blocks the hERG channel at the pore of the channel.

• Journal of Electrical Engineering and Technology
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• 제3권4호
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• pp.566-570
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• 2008

Vertical nanowire SGFETs(Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects. This paper presents design and characterization of a differential pair amplifier using NMOS and PMOS SGFETs with a 10nm channel length and a 2nm channel radius. The amplifier dissipates $5{\mu}W$ power and provides 5THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5V, and a distortion better than 3% from a 1.8V power supply and a 20aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40dBm and -52dBm, respectively, and the 3rd order intermodulation is -24dBm for a two-tone input signal with 10mV amplitude and 10GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation high speed analog and VLSI technologies.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 춘계종합학술대회
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• pp.317-320
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• 2001

본 논문에서는 Si-기반 나노채널 nMOSFET의 문턱전압에 관하여 분석하였다. 본 논문에서 연구된 소자는 180nm의 n-채널 MOSFET을 기준으로 30 nm까지의 게이트 길이를 가진 소사를 정전압 스켈링 이론에 따라 스켈링하였다. 이들 소자들은 드레인 영역에서의 전계크기 감소와 단채널 효과를 줄이기 위해 LDD(lightly doped drain) 구조를 사용하였으며 이들 소자의 문턱전압을 조사ㆍ분석하였다. 이러한 해석은 IC응용의 한계에 대한 분석을 제공할 것이며 VLSI의 기본 데이터로 활용될 수 있을 것이다.

• 대한기계학회논문집B
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• 제22권1호
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• pp.34-49
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• 1998

In this study, turbulent flows in a grooved channel are numerically investigated by Large Eddy Simulation (LES). Especially, a parametric study is carried out to study effects of length and depth of a groove on large-scale flow structures. For one test case, comparison of LES results with those of DNS reveals a good agreement even though the number of grid points of LES is only 6.5% of that of DNS. This confirms that LES is a suitable tool for a parametric study of turbulent flows. The subsequent parametric study using LES shows that the large-scale turbulent structures are significantly affected by the geometry of the groove. Especially, when the length of the groove is short such that the recirculation region occupies the entire groove, the turbulent flow in the groove becomes very weak in both mean and fluctuation quantities.

• 한국전기전자재료학회논문지
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• 제15권3호
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• pp.233-237
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• 2002

A giga-bit DRAM(dynamic random access memory) technology with W/WNx/poly-Si dual gate electrode is presented in 7his papers. We fabricated $0.16\mu\textrm{m}$ CMOS using this technology and succeeded in suppressing short-channel effects. The saturation current of nMOS and surface-channel pMOS(SC-pMOS) with a $0.16\mu\textrm{m}$ gate was observed 330 $\mu\A/\mu\textrm{m}$ and 100 $\mu\A/\mu\textrm{m}$ respectively. The lower salutation current of SC-pMOS is due to the p-doped poly gate depletion. SC-pMOS shows good DIBL(dram-induced harrier lowering) and sub-threshold characteristics, and there was no boron penetration.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.