• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.63-67
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• 2003

This paper proposes a new BLSA(Bit Line Sense Amplifier) for MRAM. Current BLSA employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed BLSA simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speedas the latch-type BLSA in simulation and occupies only 85% of the area taken by the latch-type BLSA.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1555-1557
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• 2002

We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.1-8
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• 2000

In this paper, design of sense amplifier for a flash memory minimizing bit line disturbance due to common bit line is presented. There is a disturbance problem at output modes by using common bit line, when the external devices access an internal flash memory. This phenomenon is resulted form hot carrier between floating gates and bit lines by thin oxide thickness. To minimize bit line disturbance, lower it line voltage is required and need sense amplifier to detect data existence in lower bit line voltage. Proposed circuits is operated at lower bit line voltage and we fabricated a embedded flash memory MCU using 0.6u technology.

• Journal of IKEEE
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• v.17 no.3
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• pp.260-266
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• 2013

The open bit line is vulnerable to noise compared to the folded bit line when read/write for the DRAM. According to the increasing DRAM densities, the core circuit operating conditions is exacerbated by the noise when it comes to the open bit line 6F2(F : Feature Size) structure. In this paper, the interference effects were analyzed by the data patterns between the bit line by experiments. It was beyond the scope of existing research. 68nm Tech. 1Gb DDR2, Advan Tester used in the experiments. The noise effects appears the degrade of internal operation margin of DRAM. This paper investigates sense amplifier power line splits by experiments. The noise can be improved by 0.2ns(1.3%)~1.9ns(12.7%), when the sense amplifier power lines split. It was simulated by 68nm Technology 1Gb DDR2 modeling.

• BMB Reports
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• v.32 no.3
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• pp.266-272
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• 1999

The insulin-like growth factor (IGF) system consisting of IGF-I, IGF-II, IGF-receptors, and IGF-binding proteins (IGFBP) regulates the proliferation of a variety of cancer cell types. To examine whether a decrease in endogenous IGFBP-3 stimulates proliferation or inhibits differentiation, Caco-2 cells, a human colon adenocarcinoma cell line, were stably transfected with an anti-sense IGFBP-3 expression construct or pcDNA3 vector as control. Accumulation of IGFBP-3 mRNA and secretion of IGFBP-3 into serum-free conditioned medium, 9 days after plating, were significantly lower in Caco-2 cell clones transfected with anti-sense IGFBP-3 cDNA compared to the controls. The anti-sense clones grew at a similar rate to the controls for 8 days after plating, but achieved a higher final density between days 10 and 12. The levels of sucrase-isomaltase mRNA, a marker of enterocyte differentiation of Caco-2 cells, were lower in the anti-sense clones examined on day 9. In conclusion, proliferation of Caco-2 cells can be stimulated by lowering endogenously-produced IGFBP-3.

• The Research Journal of the Costume Culture
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• v.19 no.3
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• pp.650-660
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• 2011

Purpose of this study is to explore: 1) the difference in color sensibility evaluation, color attractiveness, and attitude toward the product, 2) the difference in the effect of color sensibility evaluation on color attractiveness, and 3) the difference in the effect of color sensibility evaluation on attitude toward the product between the identical clothing product presented in on-line and off-line settings. Experimental method was applied with 230 male and female university students using stimuli of an on-line site as well as an off-line window display presenting the same white t-shirts. Color sensibility factors of white t-shirt were hedonic, stimulating, active, and spatial senses. These color sensibility factors of the clothing product affected product color attractiveness as well as attitude toward the product. Although there were not differences in color sensibility evaluation, product attractiveness, and attitude toward the product between items presented in on-line and off-line settings, difference was found in the effect of color sensibility on the color attractiveness and attitude toward the product. The effect of color sensibility on color attractiveness and attitude toward the product was stronger in on-line than in off-line setting. Hedonic sense was the most important factor influencing attractiveness of product color and attitude toward the product. In addition, spatial sense affected attractiveness of product color in on-line setting; and stimulating sense impacted attitude toward the product in off-line setting. Based on the results implications were generated.

• Journal of IKEEE
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• v.20 no.2
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• pp.167-170
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• 2016

Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.877-880
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• 1989

Described is a DC voltage regulator of new type where an optical fiber is used as a sense line to transmit the PFM signal, which represents the load voltage and its change, from the load to the controller so as to make the equivalent sense-line length short. The prototype version provides a load voltage change rate of 2.3% over the current range of 0A to 5A at 15V DC, with an output impedance of 0.06ohm.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.