Journal of Electrical Engineering and information Science

The Korean Institute of Electrical Engineers (대한전기학회)
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A Multi-Point Sense Amplifier and High-Speed Bit-Line Scheme for Embedded SRAM

  • Published : 1998.06.01
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Abstract

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

Keywords

References

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