• 반도체디스플레이기술학회지
• /
• 제19권3호
• /
• pp.55-60
• /
• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 반도체디스플레이기술학회지
• /
• 제11권3호
• /
• pp.1-6
• /
• 2012

In this paper, inspection system based on optical scanning mechanism is designed and developed for solar cell wafer. It consists of optical scanning mechanism, NIR camera optics, machinery and control system, algorithm of defect detection and software. Optical scanning mechanism is composed of geometrical camera optics and structured hybrid illumination system. It is used to inspection of surface defects. NIR camera optics is used for inspection of defects inside solar cell wafer. It is shown that surface and internal micro defects can be detected in developed inspection system for solar cell wafer.

• 제어로봇시스템학회논문지
• /
• 제19권12호
• /
• pp.1072-1080
• /
• 2013

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2013년도 춘계학술대회 논문집
• /
• pp.651-652
• /
• 2013

• 대한산업공학회지
• /
• 제41권3호
• /
• pp.267-274
• /
• 2015

In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

• 한국정밀공학회지
• /
• 제20권12호
• /
• pp.105-114
• /
• 2003

In this study, a dicing machine with vision system was built and an algorithm for automatic alignment was developed for dual camera system. The system had a macro and a micro inspection tool. The algorithm was formulated from geometric relations. When a wafer was put on the cutting stage within certain range, it was inspected by vision system and compared with a standard pattern. The difference between the patterns was analyzed and evaluated. Then, the stage was moved by x, y, $\theta$ axes to compensate these differences. The amount of compensation was calculated from the result of the vision inspection through the automatic alignment algorithm. The stage was moved to the compensated position and was inspected by vision for checking its result again. Accuracy and validity of the algorithm was discussed from these data.

• 반도체디스플레이기술학회지
• /
• 제12권2호
• /
• pp.57-61
• /
• 2013

This paper presents adaptive neuro-fuzzy inference based defect detection method for various defect types, such as micro-crack, fingerprint and contamination, in heterogeneously textured surface of polycrystalline solar wafers. Polycrystalline solar wafer consists of various crystals so the surface of solar wafer shows heterogeneously textures. Because of this property the visual inspection of defects is very difficult. In the proposed method, we use local binary feature and fuzzy reasoning for defect detection. Experimental results show that our proposed method achieves a detection rate of 80%~100%, a missing rate of 0%~20% and an over detection (overkill) rate of 9%~21%.

• 전기학회논문지P
• /
• 제55권4호
• /
• pp.167-175
• /
• 2006

This paper presents a method to segment semiconductor wafer ID on poor quality images. The method is based on multiple templates and normalized gray-level correlation (NGC) method. If the lighting condition is not so good and hence, we can not control the image quality, target image to be inspected presents poor quality ID and it is not easy to identify and then recognize the ID characters. Conventional several method to segment the interesting ID regions fails on the bad quality images. In this paper, we propose a multiple template method, which uses combinational relation of multiple templates from model templates to match several characters of the inspection images. To find out the optimal solution of multiple template model in ID regions, we introduce newly-developed snake algorithm. Experimental results using images from real FA environment are presented.

• 반도체디스플레이기술학회지
• /
• 제22권2호
• /
• pp.81-86
• /
• 2023

Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• 제18권8호
• /
• pp.2366-2380
• /
• 2024

In this study, a high-speed template matching system is proposed for wafer-vision alignment. The proposed system is designed to rapidly locate markers in semiconductor equipment used for wafer-vision alignment. We optimized and implemented a template-matching algorithm for the high-speed processing of high-resolution wafer images. Owing to the simplicity of wafer markers, we removed unnecessary components in the algorithm and designed the system using a field-programmable gate array (FPGA) to implement high-speed processing. The hardware blocks were designed using the Xilinx ZCU104 board, and the pyramid and matching blocks were designed using programmable logic for accelerated operations. To validate the proposed system, we established a verification environment using stage equipment commonly used in industrial settings and reference-software-based validation frameworks. The output results from the FPGA were transmitted to the wafer-alignment controller for system verification. The proposed system reduced the data-processing time by approximately 30% and achieved a level of accuracy in detecting wafer markers that was comparable to that achieved by reference software, with minimal deviation. This system can be used to increase precision and productivity during semiconductor manufacturing processes.