• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.9
• /
• pp.729-734
• /
• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Journal of the Semiconductor & Display Technology
• /
• v.19 no.1
• /
• pp.79-84
• /
• 2020

Unlike a printing process, it is difficult to pattern organic thin films in the longitudinal (coating) direction using a coating process. In this paper, we have investigated the feasibility of patterning organic thin films using needles. To this end, we have slot-coated an aqueous poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) solution in the form of a fine stripe or large area and then applied the dual needle; one for discharging the main solvent of the underlying thin film and the other for sucking the dissolved thin film. We have found that the pattern width and depth increase as the moving speed of the plate decreases. However, it is observed that the sidewall slope is very gentle (the length of the slope is of the order of 200 ㎛) due to the fact that the discharged main solvent is widely spread and then isotropic etching occurs. With this scheme, we have also demonstrated that a fine stripe can be obtained by scanning the dual needle closely. To demonstrate its applicability to solution-processable organic light-emitting diodes (OLEDs), we have also fabricated OLED with the patterned PEDOT:PSS stripe and observed the insulation property in the strong light-emitting stripe.

• Journal of the Korean Institute of Gas
• /
• v.24 no.5
• /
• pp.74-81
• /
• 2020

In general, when manufacturing a semiconductor, a number of hazardous and dangerous substances such as flammability, toxic, and corrosiveness are used. In particular, semiconductors are manufactured using specialty gas in processes such as CVD and etching. The specialty gas is filled in a container in the state of compressed or liquefied gas, and a gas cylinder cabinet is used as a facility for supplying this specialty gas to the semiconductor manufacturing process. When a accident occurs in the gas supply system, gas is released through a pressure release device installed in the gas cylinder to secure the safety of the supply system. In this case, the gas released inside the gas cabinet, there is a risk of leaking to the outside. After that, by analyzing the gas flow in the gas cabinet, it is intended to identify the risk associated with leak and to provide measures to prevent accidents.

• Proceedings of the KIEE Conference
• /
• 1996.07c
• /
• pp.2004-2006
• /
• 1996

A thermally driven polysilicon micro actuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS (tetracthylorthosilicate) as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE (vapor phase etching) process was also used as an effective release method for the elimination of sacrificial TEOS layer. The thickneas of polysilicon is $2{\mu}m$ and the lengths of active and passive polysilicon cantilevers are $500{\mu}m$ and $260{\mu}m$, respectively. The actuation is incurred by die thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon micro actuator was experimentally conformed as large as $21{\mu}m$ at the input voltage level of 10V and 50Hz square wave. The actuating characteristics are investigated by simulating the phenomena of heat transfer and thermal expansion in the polysilicon layer. The displacement of actuator is analyzed to be proportional to the square of input voltage. These micro actuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as micro relay, which requires large displacement or contact force but relatively slow response.

• Journal of the Semiconductor & Display Technology
• /
• v.12 no.3
• /
• pp.19-22
• /
• 2013

The purpose of this study is to develop a system that can monitor the amounts of energy consumption during CVD and etching process for semiconductor manufacturing. Specifically, this system is designed to measure the $CO_2$ emission amounts quantitatively by measuring the flow rate of gas used and amount of power consumed during the processes. The processes of CVD equipment can be classified generally into processing step and cleaning step and all the two steps were monitored. In CVD and etcher equipments, various gases including Ar and $O_2$ are used, but Ar, $O_2$ and He were monitored with the use of the LCI data of Korea Environmental Industry & Technology Institute and carbon emission coefficients of EcoInvent. As a result, it was found that the carbon emission amounts of CVD equipment for Ar, $O_2$ and He were $0.030kgCO_2/min$, $4.580{\times}10^{-3}kgCO_2/min$ and $6.817{\times}10^{-4}kgCO_2/min$, respectively and those of etcher equipment for Ar and $O_2$ are $5.111{\times}10^{-3}kgCO_2/min$ and $7.172kgCO_2/min$, respectively.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.6
• /
• pp.1995-2003
• /
• 2014

Power semiconductor devices have been the major backbone for high-power electronic devices. One of important parameters in view of power semiconductor devices often characterize with a high breakdown voltage. Therefore, many efforts have been made, since the development of the Insulated Gate Bipolar Transistor (IGBT), toward having higher level of breakdown voltage, whereby the typical design thereof is focused on the structure using the field ring. In this study, in an attempt to make up more optimized field-ring structure, the characteristics of the field ring were investigated with the use of theoretical arithmetic model and methodologically the design of experiments (DOE). In addition, the IGBT having the field-ring structure was designed via simulation based on the finding from the above, the result of which was also analyzed. Lastly, the current study described the trench field-ring structure taking advantages of trench-etching process having the improved field-ring structure, not as simple as the conventional one. As a result of the simulation, it was found that the improved trench field-ring structure leads to more desirable voltage divider than relying on the conventional field-ring structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.57-58
• /
• 2006

In MIM (metal insulator metal) capacitor, Ru (ruthenium) has been suggested as new bottom electrode due to its excellent electrical performance, a low leakage of current and compatibility to the high dielectric constant materials. In this case of Ru bottom electrode, CMP (chemical mechanical planarization) process was needed m order to planarize and isolate the bottom electrode. In this study, the effect of chemical A on polishing and etching behavior was investigated as functions of chemical A concentration, abrasive particle and pressure. Chemical A was used as oxidant and etchant. The thickness of passivation layer on the treated Ru surface increased with the increase of chemical A concentration. The etch rate and removal rate of Ru were increased by the addition of chemical A. The removal rate was highest m slurry of pH 9 with the addition of 0.1 M chemical A and 2 wt% alumina at 4 psi. The maximum removal rate is about 80 nm/min.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2001.04a
• /
• pp.1117-1120
• /
• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Journal of Electrochemical Science and Technology
• /
• v.7 no.1
• /
• pp.52-57
• /
• 2016

Nanoporous-layer-covered TiO₂ nanotube arrays (Type II TNTs) were fabricated by two-step electrochemical anodization. For comparison, conventional TiO₂ nanotube arrays (Type I TNTs) were also prepared by one-step electrochemical anodization. Types I and II TNTs were detached by selective etching and then transferred successfully to a transparent F-doped SnO₂ (FTO) substrate by a sol-gel process. Both FTO/Types I and II TNTs allowed front side illumination to exhibit incident photon-to-current efficiencies (IPCEs) in the long wavelength region of 300 to 750 nm without the absorption of light by the iodine-containing electrolyte. The Type II TNT exhibited longer electron lifetime and faster charge transfer than the Type I TNT because of its relatively fewer defect states. These beneficial effects lead to a high overall energy conversion efficiency (5.32 %) of the resulting dye-sensitized solar cell.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.4
• /
• pp.13-18
• /
• 2010

Extreme ultraviolet (EUV) lithography using 13.5 nm wavelengths is expected to be adopted as a mass production technology for 32 nm half pitch and below. One of the new issues introduced by EUV lithography is the shadowing effect. Mask shadowing is a unique phenomenon caused by using mirror-based mask with an oblique incident angle of light. This results in a horizontal-vertical (H-V) biasing effect and ellipticity in the contact hole pattern. To minimize the shadowing effect, a refilled mask is an available option. The concept of refilled mask structure can be implemented by partial etching into the multilayer and then refilling the trench with an absorber material. The simulations were carried out to confirm the possibility of application of refilled mask in 32 nm line-and-space pattern under the condition of preproduction tool. The effect of sidewall angle in refilled mask is evaluated on image contrast and critical dimension (CD) on the wafer. We also simulated the effect of refilled absorber thickness on aerial image, H-V CD bias, and overlapping process window. Finally, we concluded that the refilled absorber thickness for minimizing shadowing effect should be thinner than etched depth.