• 제목/요약/키워드: Semiconductor equipment

검색결과 868건 처리시간 0.022초

전해연마면의 표면경도 향상을 위한 플라즈마 이온질화 처리법에 관한 실험적 연구 (A experimental study about plasma ion treatment to improve hardness of electro-polished surface)

  • 김진범;홍필기;서태일;손창우
    • Design & Manufacturing
    • /
    • 제13권1호
    • /
    • pp.13-18
    • /
    • 2019
  • The size and prospects of the domestic semiconductor equipment market are increasing every year. In the case of various parts used inside semiconductor equipments, high durability such as high strength and abrasion resistance is demanded. Particularly, the gases used in semiconductor production processes are toxic. In order to prevent such toxic gas leakage, a precision processing technique and a surface treatment technique for preventing corrosion are required. Electro-polishing is an electro-chemical method of polishing a metal surface to make it smooth and polished. Electro-polishing is mainly used in the finishing process of metal surface. Unlike mechanical polishing, electro-polishing is used in many fields, such as fine chemical etching equipment, since no damaged layer or burr, fine polishing groove and particles are generated. However, in order to withstand the gas used in the semiconductor equipment, the parts must have high corrosion resistance. However, the surface hardness generally become lowered through electro-polishing. Therefore, in this study, surface hardness were experimentally observed before and after electro-polishing. Then, a method of improving hardness by preparing a nitrided layer by plasma ion nitriding treatment.

AHP 및 Fuzzy 의사결정 모형을 활용한 반도체 장치라인의 CTP 선정 방법론 개발 (Development of CTP Selection Methodology of Semiconductor Equipment Line Using AHP and Fuzzy Decision Model)

  • 정재환;김정섭;김여진;이종환
    • 반도체디스플레이기술학회지
    • /
    • 제20권2호
    • /
    • pp.6-13
    • /
    • 2021
  • Cases and studies on the selection method of CTQ are relatively active, but there are few cases or studies on the selection method of CTP which is important in the device industry. In fact, many companies simply select and manage CTP from the point of contact based on their experience and intuition. The purpose of this study is to present an evaluation model and a mathematical decision model for rational and systematic CTP selection to improve the process quality of semiconductor equipment lines. In the evaluation model, AHP (Analytic Hierarchy Process) analysis technique was applied to show objective and quantitative figures, and Fuzzy decision-making model was used to solve the ambiguity and uncertainty in the decision-making process. Decision Value (DV) was presented. The subjects were 22 process factors managed in the Plating Process that the representative equipment line can do. As a result, the evaluation model proposed in this study can support more efficient and effective decision-making for process quality improvement by more objectively measuring the problem of subjective CTP selection in manufacturing sites.

DDR2 SDRAM을 이용한 비메모리 검사장비에서 정시성을 보장하기 위한 메모리 컨트롤러 개발 (Development of Memory Controller for Punctuality Guarantee from Memory-Free Inspection Equipment using DDR2 SDRAM)

  • 전민호;신현준;강철규;오창헌
    • 한국항행학회논문지
    • /
    • 제15권6호
    • /
    • pp.1104-1110
    • /
    • 2011
  • 현재의 반도체 검사장비는 테스트 패턴 프로그램을 위한 메모리로 시스템 설계가 간단하고 리프레시가 필요 없는 SRAM(static random access memory) 모듈을 채용하고 있다. 그러나 SRAM 모듈을 이용한 시스템 구성은 용량이 커질수록 장비의 부피가 증가하기 때문에 메모리 대용량화 및 장비의 소형화에 걸림돌이 되고 있다. DRAM(dynamic random access memory)을 이용하여 반도체 검사 장비를 제작할 경우 SRAM 보다 비용과 장비의 면적이 줄어드는 장점이 있지만 DRAM의 특성 상 메모리 셀 리프레시가 필요하여 정시성을 보장해야 하는 문제가 있다. 따라서 본 논문에서는 이러한 문제를 해결하기 위해 DDR2 SDRAM(double data rate synchronous dynamic random access memory)을 이용한 비메모리 검사장비에서 정시성을 보장해 주는 알고리즘을 제안하고 알고리즘을 이용한 메모리 컨트롤러를 개발하였다. 그 결과, DDR2 SDRAM을 이용할 경우 SRAM을 이용할 때 보다 가격과 면적이 줄어들어 가격측면에서는 13.5배 그리고 면적측면에서는 5.3배 이득이 있음을 확인하였다.

반도체·FPD 제조설비와 클린룸의 RISK 최소화를 위한 폭발위험장소 설정 모델링에 관한 연구 (A Study of Explosion Hazard Proof Modeling for Risk Minimization to Semiconductor & FPD Manufature Equipment and Clean Room)

  • 노현석;우인성;황명환;우정환
    • 한국가스학회지
    • /
    • 제22권1호
    • /
    • pp.78-85
    • /
    • 2018
  • 본 연구를 통하여 반도체 FPD 제조설비 및 클린룸에 관련한 설비의 위험성분석과 그에 대한 근원적인 안전대책을 연구하고, 설비 및 환경의 특수성을 고려한 방폭 설계 모델링화를 검토하여 관련 설비의 설계 및 제작에 기술적인 기준과 근거로 활용하고자 하며, 아래와 같은 성과로서 향후 반도체 FPD 산업의 기술적 기준 수립 및 관련 산업에 기여할 것으로 생각한다. 1) 관련 국제 기술규격과 법령, 설비의 특성을 반영한 FAB 장비의 최적화된 폭발위험장소의 모델링 도출 2) FAB 장비 및 클린 룸의 특성을 고려한 위험설비의 안전성 확보 (Fool-Proof와 Fail Safe)를 위한 안전시스템 구축방안과 안전기준 및 대책 도출 3) 향후 FAB 장비의 방폭 설계에 대한 가장 효율적인 기준 적용을 통한 신규 FAB 장비의 방폭 성능의 유연성 확보하고 수립된 안전기준을 통한 설비와 안전시스템의 신뢰성 검증 절차 운영을 위한 "안전인증제도"의 자율적 향상화.

인공면역체계를 이용한 플라즈마 증착 장비의 유량조절기 오류 검출 실험 연구 (An Algorithm Study to Detect Mass Flow Controller Error in Plasma Deposition Equipment Using Artificial Immune System)

  • 유영민;정지윤;조나현;박소은;홍상진
    • 반도체디스플레이기술학회지
    • /
    • 제20권4호
    • /
    • pp.161-166
    • /
    • 2021
  • Errors in the semiconductor process are generated by a change in the state of the equipment, and errors usually arise when the state of the equipment changes or when parts that make up the equipment have flaws. In this investigation, we anticipated that aging of the mass flow controller in the plasma enhanced chemical vapor deposition SiO2 thin film deposition method caused a minute flow rate shift. In seven cases, fourier transformation infrared film quality analysis of the deposited thin film was used to characterize normal and pathological processes. The plasma condition was monitored using optical emission spectrometry data as the flow rate changed during the procedure. Preprocessing was used to apply the collected OES data to the artificial immune system algorithm, which was then used to process diagnosis. Through comparisons between datasets, the learning algorithm compared classification accuracy and improved the method. It has been confirmed that data characterized as a normal process and abnormal processes with differing flow rates may be discriminated by themselves using the artificial immune system data mining method.

준 경험기법을 이용한 고집적 반도체공장의 미진동 제어를 위한 구조물의 동적설계에 관한 연구 (A Study on the Structural Dynamic Design for Sub-micro Vibration Control in High Class Semiconductor Factor by Semi-Empirical Method)

  • 이홍기;백재호;원영재;박해동;김두훈
    • 소음진동
    • /
    • 제9권6호
    • /
    • pp.1227-1233
    • /
    • 1999
  • Modern technology depends on the reliability of extremely high technology equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a nanometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. This paper deals with the structural dynamic design in high class semiconductor factory in order to be satisfied more strict vibration criteria for high sensitive equipment.

  • PDF

반도체 장비 부품의 Ti/TiN 흡착물 세정 공정 연구 (A Study on Cleaning Processes for Ti/TiN Scales on Semiconductor Equipment Parts)

  • 유정주;배규식
    • 반도체디스플레이기술학회지
    • /
    • 제3권2호
    • /
    • pp.11-15
    • /
    • 2004
  • Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

  • PDF

스마트제조시스템의 설비인자 분석 (Analysis of Equipment Factor for Smart Manufacturing System)

  • 안재준;심현식
    • 반도체디스플레이기술학회지
    • /
    • 제21권4호
    • /
    • pp.168-173
    • /
    • 2022
  • As the function of a product is advanced and the process is refined, the yield in the fine manufacturing process becomes an important variable that determines the cost and quality of the product. Since a fine manufacturing process generally produces a product through many steps, it is difficult to find which process or equipment has a defect, and thus it is practically difficult to ensure a high yield. This paper presents the system architecture of how to build a smart manufacturing system to analyze the big data of the manufacturing plant, and the equipment factor analysis methodology to increase the yield of products in the smart manufacturing system. In order to improve the yield of the product, it is necessary to analyze the defect factor that causes the low yield among the numerous factors of the equipment, and find and manage the equipment factor that affects the defect factor. This study analyzed the key factors of abnormal equipment that affect the yield of products in the manufacturing process using the data mining technique. Eventually, a methodology for finding key factors of abnormal equipment that directly affect the yield of products in smart manufacturing systems is presented. The methodology presented in this study was applied to the actual manufacturing plant to confirm the effect of key factors of important facilities on yield.

A Dual-Level Knowledge-Based Synthesis System for Semiconductor Chip Encapsulation

  • Yong Jeong, Heo
    • 한국반도체및디스플레이장비학회:학술대회논문집
    • /
    • 한국반도체및디스플레이장비학회 2003년도 추계학술대회 발표 논문집
    • /
    • pp.154-159
    • /
    • 2003
  • Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

  • PDF