• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.4
• /
• pp.276-281
• /
• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. Generally most of field effect concentrations shows on the edge of power devices. Can be improve the breakdown characteristic using edge termination technology. In this paper, considering the variables that affect the breakdown voltage and optimization of parameters result for 600 V Super Junction MOSFET Field ring.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.12
• /
• pp.2234-2237
• /
• 2008

Approximate equations for cylindrical breakdown voltages of planar pn junctions are proposed and verified. The equations show good agreement with the Baliga's results for $r_{j}/Wpp{\leqq}0.3$ and with numerical results for $r_{j}/Wpp{\geqq}0.3$ within 1% error. Sensitivity of the breakdown voltage with respect to the doping concentrations is successfully derived using the approximate equations. The sensitivity formula can be utilized in the area of tolerance design of power semiconductor devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.3
• /
• pp.165-169
• /
• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.1
• /
• pp.28-32
• /
• 2023

Recently, the use of stable lithium nanostructures as substrates and electrodes for secondary batteries can be a fundamental alternative to the development of next-generation system semiconductor devices. However, lithium structures pose safety concerns by severely limiting battery life due to the growth of Li dendrites during rapid charge/discharge cycles. Also, enabling long cyclability of high-voltage oxide cathodes is a persistent challenge for all-solid-state batteries, largely because of their poor interfacial stabilities against oxide solid electrolytes. For the development of next-generation system semiconductor devices, solid electrolyte nanostructures, which are used in high-density micro-energy storage devices and avoid the instability of liquid electrolytes, can be promising alternatives for next-generation batteries. Nevertheless, poor lithium ion conductivity and structural defects at room temperature have been pointed out as limitations. In this study, a low-dimensional Graphene Oxide (GO) structure was applied to demonstrate stable operation characteristics based on Li+ ion conductivity and excellent electrochemical performance. The low-dimensional structure of GO-based solid electrolytes can provide an important strategy for stable scalable solid-state power system semiconductor applications at room temperature. The device using uncoated bare NCA delivers a low capacity of 89 mA h g-1, while the cell using GO-coated NCA delivers a high capacity of 158 mA h g−1 and a low polarization. A full Li GO-based device was fabricated to demonstrate the practicality of the modified Li structure using the Li-GO heterointerface. This study promises that the lowdimensional structure of Li-GO can be an effective approach for the stabilization of solid-state power system semiconductor architectures.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2002.11a
• /
• pp.99-99
• /
• 2002

• Journal of Institute of Control, Robotics and Systems
• /
• v.7 no.10
• /
• pp.837-842
• /
• 2001

In this paper, we design and implement the DC characteristic measurement system for semiconductor devices. The proposed system is composed of 4 SMU(Source and Measure Unit) channels. Various efforts in hardware and software have been made to reduce the measurement errors. Internal and external sources of errors in measurement system especially in pA range measurement have been identified and removed. Also, various digital signal processing techniques are developed. Calibration is executed under the control of microprocessor periodically. Experimental results show that the implemented system can measure the DC characteristic of semiconductor devices with less than 0.2% error in various voltage and current source/measurement range.

• Proceedings of the KAIS Fall Conference
• /
• 2010.11a
• /
• pp.107-109
• /
• 2010

화석연료 사용으로 발생한 환경 문제와 에너지원 고갈로 생성된 새로운 청정에너지에 대한 중요성은 시간이 지나면서 더욱더 증가해 가고 있다. 청정에너지로 알려져 있는 많은 에너지원 중에 태양의 빛에너지를 전기적 에너지로 변환하여 활용하기 위한 연구는 상당히 많이 이루어지고 있다. 태양전지는 공해가 적고, 자원이 무한적이며 반영구적인 수명을 가지고 있어 일부 에너지 문제에 도움을 줄 수 있는 에너지원으로 평가받고 있다. 태양전지 기술 개발 방향은 전지의 변환효율을 높이는 방향과 공정 개발 원가를 줄이는방향의 연구들로 진행되어 오고 있다. 태양전지의 변환 효율은 새로운 물질의 개발과 공정 개발을 통하여 연구가 진행되고 있으며, 발전해온 많은 반도체 기술을 통하여 많은 부분 향상되어 오고 있다. 하지만, 반도체 기술 중에 도핑 기술은 많은 부분을 연구되어 왔지만, 아직도 쉽지만은 않은 기술이다. 이러한 기술이 안정화되지 않고서는 높은 효율의 태양전지의 개발은 어려운 일이다. 본 연구에서는 태양전지 제작하는 공정을 단순화 하고 그 공정 중에 어려운 공정으로 알려진 도핑공정에 대한 연구를 진행하였다. 대양한 공정 조건으로 연구가 이루어 졌으며, 그 변화에 따른 온도변화와 소스의 농도 변화에 따른 면저항 값을 분석하였다.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.1 s.34
• /
• pp.59-63
• /
• 2005

A simulation method combined with the simulation program with integrated circuit emphasis (SPICE) and the technology computer-aided design (TCAD) has been proposed to estimate the electrical characteristics of the metal-ferroelectric-semiconductor field effect transistor (MFS/MFISFET). The complex behavior of the ferroelectric property was analyzed and surface potential of the channel region in the MFS gate structure was calculated with the numerical TCAD method. Since the calculated surface potential is equivalent with the surface potential obtained with the SPICE model of the conventional MOSFET, we can obtain the current-voltage characteristics of MFS/MFISFET corresponding to the applied gate bias. Therefore, the proposed method will be very useful for the design of the integrated circuits with MFS/MFISFET memory cell devices.

• Transactions on Electrical and Electronic Materials
• /
• v.11 no.1
• /
• pp.15-19
• /
• 2010

In this paper, we discuss design considerations for an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a lateral asymmetric channel (LAC) doping profile. We employed a $0.35\;{\mu}m$ standard complementary MOSFET process for fabrication of the devices. The gates to the LAC doping overlap lengths were 0.5, 1.0, and $1.5\;{\mu}m$. The drain current ($I_{ON}$), transconductance ($g_m$), substrate current ($i_{SUB}$), drain to source leakage current ($i_{OFF}$), and channel-hot-electron (CHE) reliability characteristics were taken into account for optimum device design. The LAC devices with shorter overlap lengths demonstrated improved $I_{ON}$ and $g_m$ characteristics. On the other hand, the LAC devices with longer overlap lengths demonstrated improved CHE degradation and $I_{OFF}$ characteristics.

• Journal of Electrical Engineering and Technology
• /
• v.6 no.2
• /
• pp.280-283
• /
• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.