• 유기물자원화
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• 제31권1호
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• pp.5-14
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• 2023

연구에서는 실리카/티타니아 코어/쉘(STCS) 물질을 기반으로 환원 및 에칭을 통해 근적외선 반사율을 향상시킬 수 있는 라이다 반사형 중공구조 검은색(B-HST) 물질을 제조하였다. 또한, 에칭 폐액을 수거 및 재활용하여 합성한 실리카(e-SiO₂) 물질을 반도체 에폭시 몰딩 컴파운드용(EMC) 필러 소재로서 응용하였다. 상세히는, 연속적인 졸-겔법, 환원법 및 초음파법을 통해 제조한 B-HST 물질은 높은 NIR 반사율(31.1%)과 실제 검은색 페인트와 유사한 명도(L^*=13.2)를 나타내었으며, 이를 통해 성공적으로 라이다에 인식될 수 있는 소재가 제조되었음을 확인하였다. 추가적으로, B-HST 물질의 합성 과정에서 코어 실리카를 에칭하여 추출한 실라놀 전구체를 포함하는 에칭 폐액을 수거한 뒤, 졸-겔법을 통해 균일한 필러용 실리카로 합성하였으며, 에폭시 고분자 및 카본블랙과의 혼합을 통해 반도체 패키지용 소재인 EMC로 제조하였다. 실험으로 제조된 EMC는 상용화된 EMC 제품과 유사한 물리적-화학적 특성을 나타냄을 확인할 수 있었다. 본 연구 결과를 통해 물질의 합성과 효과적인 재활용법의 설계를 통하여 4차 산업시대에 부합하는 고부가 가치 소재들인 자율주행차 차량용 검은색 물질과 반도체용 EMC 물질들을 성공적으로 제조하고 미래 산업에서의 응용 가능성에 대해 제시하였다.

• 한국전기전자재료학회논문지
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• 제13권9호
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 반도체디스플레이기술학회지
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• 제19권1호
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• pp.79-84
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• 2020

Unlike a printing process, it is difficult to pattern organic thin films in the longitudinal (coating) direction using a coating process. In this paper, we have investigated the feasibility of patterning organic thin films using needles. To this end, we have slot-coated an aqueous poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) solution in the form of a fine stripe or large area and then applied the dual needle; one for discharging the main solvent of the underlying thin film and the other for sucking the dissolved thin film. We have found that the pattern width and depth increase as the moving speed of the plate decreases. However, it is observed that the sidewall slope is very gentle (the length of the slope is of the order of 200 ㎛) due to the fact that the discharged main solvent is widely spread and then isotropic etching occurs. With this scheme, we have also demonstrated that a fine stripe can be obtained by scanning the dual needle closely. To demonstrate its applicability to solution-processable organic light-emitting diodes (OLEDs), we have also fabricated OLED with the patterned PEDOT:PSS stripe and observed the insulation property in the strong light-emitting stripe.

• 한국가스학회지
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• 제24권5호
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• pp.74-81
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• 2020

일반적으로 반도체를 제조할 때는 인화성, 독성, 부식성의 유해·위험물질이 다수 사용되며, 특히 화학적 증착(CVD), 식각(Etch) 등의 공정에서는 특수가스를 사용하여 반도체를 제조하고 있다. 특수가스는 압축 또는 액화가스의 상태로 용기에 충전되어 있는데, 특수가스를 반도체 제조공정에 공급하는 설비로서 가스캐비닛(Gas Cylinder Cabinet)이 사용되고 있다. 이러한 가스공급시스템 내에서 실린더 이상 발생 시 배관·계측기 등 공급시스템의 안전 확보를 위해 가스실린더에 설치된 압력방출장치를 통해 가스가 방출하게 되는데, 이 경우 가스캐비닛 내부에 방출되는 가스가 캐비닛 외부로 누출될 위험성이 존재한다. 따라서 가스캐비닛 내부의 유체유동을 분석하여 누출에 따른 위험성을 파악하고 이에 대한 위험도 감소를 위한 대책을 제시하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.2004-2006
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• 1996

A thermally driven polysilicon micro actuator has been fabricated using surface micromachining techniques. It consists of P-doped polysilicon as a structural layer and TEOS (tetracthylorthosilicate) as a sacrificial layer. The polysilicon was annealed for the relaxation of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE (vapor phase etching) process was also used as an effective release method for the elimination of sacrificial TEOS layer. The thickneas of polysilicon is $2{\mu}m$ and the lengths of active and passive polysilicon cantilevers are $500{\mu}m$ and $260{\mu}m$, respectively. The actuation is incurred by die thermal expansion due to the current flow in the active polysilicon cantilever, which motion is amplified by lever mechanism. The moving distance of polysilicon micro actuator was experimentally conformed as large as $21{\mu}m$ at the input voltage level of 10V and 50Hz square wave. The actuating characteristics are investigated by simulating the phenomena of heat transfer and thermal expansion in the polysilicon layer. The displacement of actuator is analyzed to be proportional to the square of input voltage. These micro actuator technology can be utilized for the fabrication of MEMS (microelectromechanical system) such as micro relay, which requires large displacement or contact force but relatively slow response.

• 반도체디스플레이기술학회지
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• 제12권3호
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• pp.19-22
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• 2013

The purpose of this study is to develop a system that can monitor the amounts of energy consumption during CVD and etching process for semiconductor manufacturing. Specifically, this system is designed to measure the $CO_2$ emission amounts quantitatively by measuring the flow rate of gas used and amount of power consumed during the processes. The processes of CVD equipment can be classified generally into processing step and cleaning step and all the two steps were monitored. In CVD and etcher equipments, various gases including Ar and $O_2$ are used, but Ar, $O_2$ and He were monitored with the use of the LCI data of Korea Environmental Industry & Technology Institute and carbon emission coefficients of EcoInvent. As a result, it was found that the carbon emission amounts of CVD equipment for Ar, $O_2$ and He were $0.030kgCO_2/min$, $4.580{\times}10^{-3}kgCO_2/min$ and $6.817{\times}10^{-4}kgCO_2/min$, respectively and those of etcher equipment for Ar and $O_2$ are $5.111{\times}10^{-3}kgCO_2/min$ and $7.172kgCO_2/min$, respectively.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.1995-2003
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• 2014

Power semiconductor devices have been the major backbone for high-power electronic devices. One of important parameters in view of power semiconductor devices often characterize with a high breakdown voltage. Therefore, many efforts have been made, since the development of the Insulated Gate Bipolar Transistor (IGBT), toward having higher level of breakdown voltage, whereby the typical design thereof is focused on the structure using the field ring. In this study, in an attempt to make up more optimized field-ring structure, the characteristics of the field ring were investigated with the use of theoretical arithmetic model and methodologically the design of experiments (DOE). In addition, the IGBT having the field-ring structure was designed via simulation based on the finding from the above, the result of which was also analyzed. Lastly, the current study described the trench field-ring structure taking advantages of trench-etching process having the improved field-ring structure, not as simple as the conventional one. As a result of the simulation, it was found that the improved trench field-ring structure leads to more desirable voltage divider than relying on the conventional field-ring structure.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.57-58
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• 2006

In MIM (metal insulator metal) capacitor, Ru (ruthenium) has been suggested as new bottom electrode due to its excellent electrical performance, a low leakage of current and compatibility to the high dielectric constant materials. In this case of Ru bottom electrode, CMP (chemical mechanical planarization) process was needed m order to planarize and isolate the bottom electrode. In this study, the effect of chemical A on polishing and etching behavior was investigated as functions of chemical A concentration, abrasive particle and pressure. Chemical A was used as oxidant and etchant. The thickness of passivation layer on the treated Ru surface increased with the increase of chemical A concentration. The etch rate and removal rate of Ru were increased by the addition of chemical A. The removal rate was highest m slurry of pH 9 with the addition of 0.1 M chemical A and 2 wt% alumina at 4 psi. The maximum removal rate is about 80 nm/min.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 춘계학술대회 논문집
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Journal of Electrochemical Science and Technology
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• 제7권1호
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• pp.52-57
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• 2016

Nanoporous-layer-covered TiO₂ nanotube arrays (Type II TNTs) were fabricated by two-step electrochemical anodization. For comparison, conventional TiO₂ nanotube arrays (Type I TNTs) were also prepared by one-step electrochemical anodization. Types I and II TNTs were detached by selective etching and then transferred successfully to a transparent F-doped SnO₂ (FTO) substrate by a sol-gel process. Both FTO/Types I and II TNTs allowed front side illumination to exhibit incident photon-to-current efficiencies (IPCEs) in the long wavelength region of 300 to 750 nm without the absorption of light by the iodine-containing electrolyte. The Type II TNT exhibited longer electron lifetime and faster charge transfer than the Type I TNT because of its relatively fewer defect states. These beneficial effects lead to a high overall energy conversion efficiency (5.32 %) of the resulting dye-sensitized solar cell.