• Electrical & Electronic Materials
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• v.9 no.6
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• pp.584-592
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• 1996

Coupling optical modulator which on the $LiTaO_3$ substrate is fabricated by using proton exchange method and self-aligned method. Proton exchange of proton diffusion method was applied to pattern a waveguide on $LiTaO_3$ substrate. The annealing at >$400^{\circ}C$ was carded out to control waveguide width and depth. The depths of the two annealed optical waveguides, which were measured by using .alpha.-step, were 1.435 K.angs. and 1.380 K.angs. Using .alpha.-step facility, we examined that the width of waveguides is increased from 5.mu.m to 6.45 .mu.m and 6.3.mu.m due to the annealing effects. The process of proton exchange was done at 150.deg. C for 120 min, >$200^{\circ}C$ for 60 min and annealing process was done at >$400^{\circ}C$ for 90 min, >$400^{\circ}C$ for 60 min. The high speed coupling optical modulator has very good figures of merits; the measured high frequency power were achieved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.264-268
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• 1996

Directional coupling optical switch which on the LiNbO$_3$ substrate is fabricated by using proton exchange method and self-aligned method. Proton exchange of proton diffusion method was applied to pattern a waveguide on LiNbO$_3$ substrate. The annealing at 400[$^{\circ}C$] was caroled out to control waveguide width and depth. The process of proton exchange was done at 150[$^{\circ}C$] for 120[min], 200[$^{\circ}C$] for 60[min] and annealing process was done at 400[$^{\circ}C$] for 90[min], 400[$^{\circ}C$] for 60[min]. The high speed directional coupling optical switch has very good figures of merits:the measured high frequency power were achieved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.127-133
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• 1996

In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photoresist reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate form both sides of the main gate. The poly-Si channel layer below the offset oxide is protected form the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of oru new device is the offset region due to the offset oxide. our experimental reuslts show that the offset region, due to the photoresist reflow process, has been sucessfully obtained in order to fabricate the offset gated poly-Si TFTs. The maximum ON/OFF ratio occurs at the L$_{off}$ of 1.1${\mu}$m and exceeds 1X10$^{6}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.808-810
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• 2005

Inexpensive large area arrays of thin film transistors (TFTs) on flexible substrates will enable many new display products that cannot be cost effectively manufactured by conventional means. This paper presents a new approach for low cost manufacturing of electronic devices using roll-to-roll (R2R) processes exclusively. It was developed in partnership by Hewlett Packard Laboratories and Iowa Thin Film Technologies (ITFT), a solar cell manufacturer. The approach combines ITFT's unique processes for vacuum deposition and etching of semiconductors, dielectrics and metals on continuous plastic webs with a method HP has invented for the patterning and aligning the multiple layers of a TFT with sub-micron accuracy and feature size.

• Journal of the Korean institute of surface engineering
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• v.55 no.6
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• pp.328-341
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• 2022

Area selective atomic layer deposition (AS-ALD) is a bottom-up nanopattern fabrication method that can grow the ALD films only on the desired substrate areas without using photolithography and etching processes. Particularly, AS-ALD has attracted great attention in the semiconductor manufacturing process due to its advantage in reducing edge placement error by fabricating self-aligned patterns. In this paper, the basic principles and characteristics of AS-ALD are described. In addition, various approaches for achieving AS-ALD with excellent selectivity were comprehensively reviewed. Finally, the technology development to overcome the selectivity limit of AS-ALD was introduced along with future prospects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.1
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• pp.16-20
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• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.

• Transactions on Electrical and Electronic Materials
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• v.1 no.1
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• pp.40-44
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• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.5.2-5.2
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• 2009

From 10 years ago, the development of nano-devices endeavored to achieve reconstruction of information technology (IT) and nano technology (NT) industry. Among the many materials for the IT and NT industry, zinc oxide (ZnO) is a very promising candidate material for the research of nano-device development. Nano-structures of ZnO-based materials were grown easily via various methods and it attracts huge attention because of their superior electrical and optical properties for optoelectronic devices. Recently, among the various growth methods, MOCVD has attracted considerable attention because it is suitable process with benefits such as large area growth, vertical alignment, and accurate doping for nano-device fabrication. However, ZnO based nanowires grown by MOCVD process were had the principal problems of 1st interfacial layers between substrate and nanowire, 2nd a broad diameter (about 100 nm), and 3rd high density, and 4th critical evaporation temperature of Zinc precursors. In particular, the growth of high performance nanowire for high efficiency nano-devices must be formed at high temperature growth, but zinc precursors were evaporated at high temperature.These problems should be repaired for materialization of ultra high performance quantum devices with quantum effect. For this reason, we firstly proposed the growth method of vertical aligned slim MgZnO nanowires (< 10 nm) without interfacial layers using self-phase separation by introduced Mg at critical evaporation temperature of Zinc precursors ($500^{\circ}C$). Here, the self-phase separation was reported that MgO-rich and the ZnO-rich phases were spontaneously formed by additionally introduced Mg precursors. In the growth of nanowires, the nanowires were only grown on the wurzite single crystal seeds as ZnO-rich phases with relatively low Mg composition (~36 at %). In this study, we investigated the microstructural behaviors of self-phase separation with increasing the Mg fluxes in the growth of MZO NWs, in order to secure drastic control engineering of density,diameter, and shape of nanowires.

• Proceedings of the KIEE Conference
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• 2008.10a
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• pp.131-132
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• 2008

We describe a fabrication method of submicron glass trenches which have embedded metal lines for the future application of nano-scale RF MEMS devices. The glass wafer was etched using two different conditions to identify the relationship between the slope of glass trenches and the slope of photroresist. A self-aligned metal photomask and negative photroresist (PR) slope were used to insert metal lines inside the glass trenches. The PR slope patterned by backside photolithography was affected by the profile of preformed glass trenches. Gold was well fabricated in the $0.7{\mu}m$ wide trench thanks to the negative PR slope. Nano-scale glass trenches with embedded metal lines can be used as a bottom electrode in submicron beam resonators operating with a high resonant frequency.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.2-252.2
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• 2013

ZnO nanostructures have a lot of interest for decades due to its varied applications such as light-emitting devices, power generators, solar cells, and sensing devices etc. To get the high performance of these devices, the factors of nanostructure geometry, spacing, and alignment are important. So, Patterning of vertically- aligned ZnO nanowires are currently attractive. However, many of ZnO nanowire or nanorod fabrication methods are needs high temperature, such vapor phase transport process, metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy, thermal evaporation, pulse laser deposition and thermal chemical vapor deposition. While hydrothermal process has great advantages-low temperature (less than $100^{\circ}C$), simple steps, short time consuming, without catalyst, and relatively ease to control than as mentioned various methods. In this work, we investigate the dependence of ZnO nanowire alignment and morphology on si substrate using of nanosphere template with various precursor concentration and components via hydrothermal process. The brief experimental scheme is as follow. First synthesized ZnO seed solution was spun coated on to cleaned Si substrate, and then annealed $350^{\circ}C$ for 1h in the furnace. Second, 200nm sized close-packed nanospheres were formed on the seed layer-coated substrate by using of gas-liquid-solid interfacial self-assembly method and drying in vaccum desicator for about a day to enhance the adhesion between seed layer and nanospheres. After that, zinc oxide nanowires were synthesized using a low temperature hydrothermal method based on alkali solution. The specimens were immersed upside down in the autoclave bath to prevent some precipitates which formed and covered on the surface. The hydrothermal conditions such as growth temperature, growth time, solution concentration, and additives are variously performed to optimize the morphologies of nanowire. To characterize the crystal structure of seed layer and nanowires, morphology, and optical properties, X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), Raman spectroscopy, and photoluminescence (PL) studies were investigated.