• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권7호
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• pp.311-315
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• 2002

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

• 한국전기전자재료학회논문지
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• 제21권3호
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• pp.203-207
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• 2008

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 proceedings of the second asia international conference on tribology
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• pp.443-444
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• 2002

The uniformity of field oxide is critical to isolation property of device in STI, so the control of field oxide thickness in STI-CMP becomes enormously important. The loss of field oxide in shallow trench isolation comes mainly from dishing and erosion in STI-CMP. In this paper, the effect of slurries on the dishing was investigated with both blanket and patterned wafers were selected to measure the removal rate, selectivity and dishing amount. Dishing was a strong function of pattern spacing and types of slurries. Dishing was significantly decreased with decreasing pattern spacing for both slurries. Significantly lower dishing with ceria based slurry than with silica based slurry were achieved when narrow pattern spacing were used. Possible dishing mechanism with two different slurries were discussed based on the observed experimental results.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.64-64
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• 2003

고집적화된 시스템 LSI 반도체 소자 제조 공정에서 소자의 고속화 및 고성능화에 따른 배선층수의 증가와 배선 패턴 미세화에 대한 요구가 갈수록 높아져, 광역평탄화가 가능한 STI CMP(Shallow Trench Isolation Chemical-Mechanical-Polishing)공정의 중요성이 더해가고 있다. 이러한 STI CMP 공정에서 세리아 슬러리에 첨가되는 계면활성제의 농도에 따라 산화막과 질화막 사이의 연마 선택비를 제어하는 것이 필수적 과제로 등장하고 있다. 일반적인 CMP 공정에서 압력 증가에 따른 연마 제거량이 Prestonian 거동을 나타내는 반면, 연마 입자의 크기를 변화시켜 계면활성제의 농도를 달리 하였을 경우, 압력 변화에 따라 Non-Prestonian 거동이 나타나는 것을 고찰할 수 있었다. 따라서 본 연구에서는 세리아 슬러리 내에 첨가되는 계면활성 제의 농도와 연마입자의 크기를 달리한 후, 압력을 변화시킴으로 나타나는 non-Prestonian 거동에 미치는 영향에 대하여 연구하였다.

• 반도체디스플레이기술학회지
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• 제3권1호
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• pp.15-20
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• 2004

Through shallow trench isolation (STI) chemical mechanical polishing (CMP) tests, we investigated the dependence of pad surface temperature on the abrasive and additive concentrations in ceria slurry under varying pressure using blanket film wafers. The pad surface temperature after CMP increased with the abrasive concentration and decreased with the additive concentration in slurries for the constant down pressure. A possible mechanism is that the additive adsorbed on the film surfaces during polishing decreases the friction coefficient, hence the pad surface temperature gets lower with increasing the additive concentration. This difference in temperature was more remarkable for the higher concentration of abrasives. In addition, in-situ measurement of spindle motor was carried out during oxide and nitride polishing. The averaged motor current for oxide film was higher than that for nitride film, meaning the higher friction coefficient.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.211-213
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• 1999

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.723-725
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• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 추계학술대회 논문집 Vol.18
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• pp.356-357
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• 2005

Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials at their surfaces. Especially, polishing pad is considered as one of the most important consumables because of its properties. Subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure pad. Microstructure pad is designed to have uniform structure on its surface and fabricated by micro-molding technology. And then STI CMP performances such as oxide dishing and nitride corner rounding are evaluated.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 춘계총회 및 연구발표회 초록집
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• pp.156.2-156
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• 2003

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.61-61
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• 2003

CMP(Chemical Mechanical Polishing)는 VLSI의 제조공정에서 실리콘웨이퍼의 절연막내에 있는 토포그래피를 제어할 수 있는 광역 평탄화 기술이다. 또한 최근에는 실리콘웨이퍼의 나노토포그래피(Nanotopography)가 STI의 CMP 공정에서 연마 후 필름의 막 두께 변화에 많은 영향을 미치게 됨으로 중요한 요인으로 대두되고 있다. STI CMP에 사용되는 CeO$_2$ 슬러리에서 첨가되는 계면활성제의 농도에 따라서 나노토포그래피에 미치는 영향을 제어하는 것이 필수적 과제로 등장하고 있다. 본 연구에서는 STI CMP 공정에서 사용되는 CeO$_2$ 슬러리에서 계면활성제의 농도에 따른 나노토포그래피의 의존성에 대해서 연구하였다. 실험은 8 "단면연마 실리콘웨이퍼로 PETEOS 7000$\AA$이 증착 된 것을 사용하였으며, 연마 시간에 따른 나노토포그래피 의존성을 알아보기 위해 연마 깊이는 3000$\AA$으로 일정하게 맞췄다. 그리고 CMP 공정은 Strasbaugh 6EC를 사용하였으며, 패드는 IC1000/SUBA4(Rodel)이다. 그리고 연마시 적용된 압력은 4psi(Pounds per Square Inch), 헤드와 정반(table)의 회전속도는 각각 70rpm이다 슬러리는 A, B 모두 CeO$_2$ 슬러리로 입자크기가 다른 것을 사용하였고, 농도를 달리한 계면활성제가 첨가되었다. CMP 전 후 웨이퍼의 막 두께 측정은 Nanospec 180(Nanometrics)과 spectroscopic ellipsometer (MOSS-ES4G, SOPRA)가 사용되었다.