Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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A study on Relationship between Pattern wafer and Blanket Wafer for STI-CMP

STI-CMP 공정을 위한 Pattern wafer와 Blanket wafer 사이의 특성 연구

  • 김상용 (중앙대학교 전자전기공학부) ;
  • 이경태 (중앙대학교 전자전기공학부) ;
  • 김남훈 (중앙대학교 전자전기공학부) ;
  • 서용진 (대불대학교 전기전자공학부) ;
  • 김창일 (중앙대학교 전자전기공학부) ;
  • 이우선 (조선대학교 전기공학과) ;
  • 장의구 (중앙대학교 전자전기공학부)
  • Published : 1999.05.01
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Abstract

In this paper, we documented the controlling oxide removal amount on the pattern wafer using removal rate and removal thickness of blanket wafer. There was the strong correlation relationship for both(correlation factor:0.7109). So, we could confirm the repeatability as applying for STI CMP process from the obtained linear formular. As the result of repeatability test, the difference of calculated polishing time and actual polishing time was 3.48 seconds based on total 50 lots. If this time is converted into the thickness, it is from 104$\AA$ to 167$\AA$. It is possible to be ignored because it is under the process margin.

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