• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.347-350
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• 2013

By inserting a very thin metal layer of Ag between two outer oxide layers of amorphous silicon indium zinc oxide (SIZO), we fabricated a highly transparent SIZO/Ag/SIZO multilayer on a glass substrate. In order to find the optimized thickness of Ag layers, we investigated the variation of optical properties depending on Ag thickness. It was found that the transition of Ag layer from island formation to a continuous film occurred at a critical thickness. Continuity of the Ag film is very important for optical properties in SIZO/Ag/SIZO multilayer. With about 15 nm thick Ag layer, the multilayer showed a high optical transmittance of 80% at 550 nm and low emissivity in IR.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.13-15
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• 2017

Low emissivity glass for high transparency in the visible range and low emissivity in the IR (infrared) range was fabricated and investigated. The multilayers were have been fabricated, and consisted of two outer oxide layers and a middle layer of Ag as a metal layer. Oxide layers were formed by rf sputtering and metal layers were formed using by an evaporator at room temperature. SiInZnO (SIZO) film was used as an oxide layer. The OMO (oxide-metaloxide) structures of SIZO/Ag/SIZO were analyzed by using transmittance, AFM (atomic force microscopye), and XRD (X-ray diffraction). The OMO multilayer structure was designed to investigate the effect of Ag layer thickness on the optical property of the OMO structure.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1453-1454
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• 2011

We have investigated the effect of silicon contents (0~0.4 molar ratios) on the performance of solution processed silicon-indium-zinc oxide (SIZO) thin-film transistors (TFTs). Despites its solution processed channel layer, low annealed temperature below $200^{\circ}C$ in air has been used for SIZO-TFTs. The $V_{th}$ is shifted from -4.04 to 5.15 V as increasing Si ratio in the SIZO-TFTs. The positive shift of $V_{th}$ as increasing Si contents in SIZO system indicates that Si suppresses the carrier generation in the active channel layer since $V_{th}$ is defined as the voltage required accumulating sufficient charge carriers to form a conductive channel path.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.380-382
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• 2016

The mechanism for instability under PBS (positive bias stress) in amorphous SIZO (Si-In-Zn-O) thin-film transistors was investigated by analyzing the charge trapping mechanism. It was found that the bulk traps in the SIZO channel layer and the channel/dielectric interfacial traps are not created during the PBS duration. This result suggests that charge trapping in gate dielectric, and/or in oxide semiconductor bulk, and/or at the channel/dielectric interface is a more dominant mechanism than the creation of defects in the SIZO-TFTs.

• Transactions on Electrical and Electronic Materials
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• v.16 no.1
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• pp.46-48
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• 2015

Thin film transistor (TFT) with silicon indium zinc oxide (SIZO) was fabricated by solution process, and the effect of annealling temperature on the electrical performance has been explored. The performance of SIZO TFT exhibited saturation mobility of $1.37cm^2$/Vs, a threshold voltage of -7.2 V, and an on-off ratio of $1.1{\times}10^5$.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.205-205
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• 2015

최근, 비정질 산화물 반도체를 이용한 TFT는 투명성, 유연성, 저비용, 저온공정이 가능하기 때문에 차세대 flat-panel 디스플레이의 back-plane TFT로써 다양한 방면에서 연구되고 있다. 산화물 반도체 In-Zn-O-시스템에서는 Gallium (Ga)을 suppressor로 사용한 a-In-Ga-Zn-O (a-IGZO) 뿐만 아니라, Magnesium (Mg), Hafnium (Hf), Tin (Sn), Zirconium (Zr) 등의 다양한 물질이 연구되었다. 그 중 Silicon (Si)은 Ga, Hf, Sn, Zr, Mg과 같은 suppressor에 비해 구하기 쉬우며 가격적인 측면에서도 저렴하다는 장점이 있다. solution 공정으로 제작한 산화물 반도체 TFT는 진공 시스템을 사용한 공정보다 공정시간이 짧고, 저비용, 대면적화가 가능하다는 장점이 있다. 하지만, 투명하고 유연한 device를 제작하기 위해서는 저온 공정과 low thermal budget은 필수적이다. 이러한 측면에서 MWI (Microwave Irradiation)는 저온공정이 가능하며, 짧은 공정 시간에도 불구하고 IZO 시스템의 산화물 반도체의 전기적 특성 향상을 기대할 수 있는 효율 적인 열처리 방법이다. 본 연구에서는 In-Zn-O 시스템의 TFT에서 silicon (Si)를 Suppressor로 사용한 a-Si-In-Zn-O (SIZO) TFT를 제작하여 두 가지 열처리 방법을 사용하여 TFT의 전기적 특성을 확인하였다. 첫 번째 방법은 Box Furnace를 사용하여 N2 분위기에서 $600^{\circ}C$의 온도로 30분간 열처리 하였으며, 두 번째는 MWI를 사용하여 1800 W 출력 (약 $100^{\circ}C$)에 2분간 열처리 하였다. MWI 열처리는 Box Furnace 열처리에 비해 저온 공정 및 짧은 시간에도 불구하고 향상된 전기적 특성을 확인 할 수 있었다.