• Journal of the Semiconductor & Display Technology
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• v.14 no.3
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• pp.61-66
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• 2015

Recently, the major trends of NIL are high throughput and large area patterning. For UV NIL, if it can be proceeded in the non-vacuum environment, which greatly simplifies tool construction and greatly shorten process times. However, one key issue in non-vacuum environment is air bubble formation problem. In this paper, numerical analysis of bubble defect of UV NIL is performed. Fluent, flow analysis focused program was utilized and VOF (Volume of Fluid) skill was applied. For various resist-substrate and resist-mold angles, effects of velocity inlet and residual layer thickness of resist on bubble defect formation were investigated. The numerical analyses show that the increases of velocity inlet and residual layer thickness can cause the bubble defect formation, however the decreases of velocity inlet and residual layer thickness take no difference in the bubble defect formation.

• Journal of the Semiconductor & Display Technology
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• v.16 no.4
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• pp.68-74
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• 2017

Nanoimprint lithography (NIL) is a next generation technology for fabrication of micrometer and nanometer scale patterns. There have been considerable attentions on NIL due to its potential abilities that enable cost-effective and high-throughput nanofabrication to the display device and semiconductor industry. Up to now there have been a lot of researches on thermal NIL, but most of them have been focused on polymer deformation in the molding process and there are very few studies on the cooling and demolding process. In this paper a cooling process of the polymer resist in thermal NIL is analyzed with finite element method. The modeling of cooling process for mold, polymer resist and substrate is developed. And the cooling process is numerically investigated with the effects of imprinting temperature and residual layer thickness of polymer resist on stress distribution of the polymer resist. The results show that the lower imprinting temperature, the higher the maximum von Mises stress and that the thicker the residual layer, the greater maximum von Mises stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.132-132
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• 2010

In the nano-scale Si processing, patterning processes based on multilevel resist structures becoming more critical due to continuously decreasing resist thickness and feature size. In particular, highly selective etching of the first dielectric layer with resist patterns are great importance. In this work, process window for the infinitely high etch selectivity of silicon oxynitride (SiON) layers and silicon nitride (Si3N4) with EUV resist was investigated during etching of SiON/EUV resist and Si3N4/EUV resist in a CH2F2/N2/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the CH2F2 and N2 flow ratio and low-frequency source power (PLF). It was found that the CH2F2/N2 flow ratio was found to play a critical role in determining the process window for ultra high etch selectivity, due to the differences in change of the degree of polymerization on SiON, Si3N4, and EUV resist. Control of N2 flow ratio gave the possibility of obtaining the ultra high etch selectivity by keeping the steady-state hydrofluorocarbon layer thickness thin on the SiON and Si3N4 surface due to effective formation of HCN etch by-products and, in turn, in continuous SiON and Si3N4 etching, while the hydrofluorocarbon layer is deposited on the EUV resist surface.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1727-1732
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• 2008

We present a facile, yet versatile carbon nanofabrication method using electron beam lithography and resist pyrolysis. Various resist nanopatterns were fabricated using a negative electron beam resist, SAL-601, and were then subjected to heat treatment in an inert atmosphere to obtain carbon nanopatterns. Suspended carbon nanostructures were fabricated by wet-etching of an underlying sacrificial oxide layer. Free-standing carbon nanostructures, which contain 122 nm-wide, 15 nm-thick, and 2 ${\mu}m$-long nanobridges, were fabricated by resist pyrolysis and nanomachining processes. Electron beam exposure dose effects on resist thickness and pattern widening were studied. The thickness of the carbon nanostructures was thinned down by etching with oxygen plasma. An electrical biosensor utilizing carbon nanostructures as a conducting channel was studied. Conductance modulations of the carbon device due to streptavidin-biotin binding and pH variations were observed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.75-81
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• 2015

In this paper, numerical analysis by finite element method and parameter design by the Taguchi method were used to reduce warpage of a two passive components embedded double side substrate for PoP(Package on Package). The effect of thickness of circuit layers (L1, L2) and thickness of solder resist (SR_top, SR_BTM) were analyzed with 4 variations and 3 levels(minimum, average and maximum thickness) to find optimized thickness conditions. Also, paste effect of solder resist on unit area of top surface was analyzed. Finally, experiments was carried out to prove numerical analysis and the Taguchi method. Based on the numerical and experimental results, it was known that circuit layer in ball side of substrate was the most severe determining deviation for reducing warpage. Buried circuit layer in chip side, solder resist and were insignificant effects on warpage relatively. However, warpage decreased as circuit layer in ball side thickness increased but effect of solder resist and circuit layer in chip side thickness were conversely.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.4
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• pp.31-39
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• 2021

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.210-210
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• 2011

The effects of CH2F2 and N2 gas flow rates on the etch selectivity of silicon nitride (Si3N4) layers to extreme ultra-violet (EUV) resist and the variation of the line edge roughness (LER) of the EUV resist and Si3N4 pattern were investigated during etching of a Si3N4/EUV resist structure in dual-frequency superimposed CH2F2/N2/Ar capacitive coupled plasmas (DFS-CCP). The flow rates of CH2F2 and N2 gases played a critical role in determining the process window for ultra-high etch selectivity of Si3N4/EUV resist due to disproportionate changes in the degree of polymerization on the Si3N4 and EUV resist surfaces. Increasing the CH2F2 flow rate resulted in a smaller steady state CHxFy thickness on the Si3N4 and, in turn, enhanced the Si3N4 etch rate due to enhanced SiF4 formation, while a CHxFy layer was deposited on the EUV resist surface protecting the resist under certain N2 flow conditions. The LER values of the etched resist tended to increase at higher CH2F2 flow rates compared to the lower CH2F2 flow rates that resulted from the increased degree of polymerization.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.57-62
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• 2012

In this paper, numerical analysis by finite element method, parameter design by the Taguchi method and ANOVA method were used to analyze about effect of design deviations and thickness variations on warpage of FCCSP substrate. Based on the computed results, it was known that core material in substrate was the most determining deviation for reducing warpage. Solder resist, prepreg and circuit layer were insignificant effect on warpage relatively. But these results meant not thickness effect was little importance but mechanical properties of core material were very effective. Warpage decreased as Solder resist and circuit layer thickness decreased but effect of prepreg thickness was conversely. Also, these results showed substrate warpage would be increased to maximum 40% as thickness deviation combination. It meant warpage was affected by thickness tolerance under manufacturing process even if it were met quality requirements. Threfore, it was strongly recommended that substrate thickness deviation should be optimized and controlled precisely to reduce warpage in manufacturing process.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.458-458
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• 2010

The process window for the etch selectivity of silicon nitride ($Si_3N_4$) layers to extreme ultra-violet (EUV) resist and variation of line edge roughness (LER) of EUV resist were investigated durin getching of $Si_3N_4$/EUV resist structure in a dual-frequency superimposed capacitive coupled plasma (DFS-CCP) etcher by varying the process parameters, such as the $CH_2F_2$ and $N_2$ gas flow rate in $CH_2F_2/N_2$/Ar plasma. The $CH_2F_2$ and $N_2$ flow rate was found to play a critical role in determining the process window for infinite etch selectivity of $Si_3N_4$/EUV resist, due to disproportionate changes in the degree of polymerization on $Si_3N_4$ and EUV resist surfaces. The preferential chemical reaction between hydrogen and carbon in the hydrofluorocarbon ($CH_xF_y$) polymer layer and the nitrogen and oxygen on the $Si_3N_4$, presumably leading to the formation of HCN, CO, and $CO_2$ etch by-products, results in a smaller steady-state hydrofluorocarbon thickness on $Si_3N_4$ and, in turn, in continuous $Si_3N_4$ etching due to enhanced $SiF_4$ formation, while the $CH_xF_y$ layer is deposited on the EUV resist surface. Also critical dimension (and line edge roughness) tend to decrease with increasing $N_2$ flow rate due to decreased degree of polymerization.