Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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A Study on Robust Design of PCB for Package on Package by Numerical Analysis with Unit and Substrate Level to Reduce Warpage

수치해석을 이용한 Package on Package용 PCB의 Warpage 감소를 위한 Unit과 Substrate 레벨의 강건설계 연구

  • Cho, Seunghyun (Department of Mechanical Engineering, Dongyang Mirae University) ;
  • Kim, Yun Tae (Department of Mechanical Engineering, Dongyang Mirae University) ;
  • Ko, Young Bae (Sustainable Technology and Wellness R&D Group, KITECH)
  • 조승현 (동양미래대학교 기계공학과) ;
  • 김윤태 (동양미래대학교 기계공학과) ;
  • 고영배 (한국생산기술연구원 청정웰빙연구그룹)
  • Received : 2021.11.19
  • Accepted : 2021.12.06
  • Published : 2021.12.30
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Abstract

In this paper, warpage analysis that separates PCB for PoP (Package on Package) into unit and substrate using FEM (Finite Element Method), analysis of the effect of layer thickness on warpage, and SN (Signal-to-Noise) ratio by Taguchi method was carried. According to the analysis result, the contribution of the circuit layer on warpage was very high in the unit PCB, and the contribution of the outer layer was particularly high. On the other hand, the substrate PCB had a high influence of the circuit layer on warpage, but it was relatively low compared to the unit PCB, and the influence of the solder resist was rather increased. Therefore, considering the unit PCB and the substrate PCB at the same time, it is desirable to design the PCB for PoP layer-by-layer structure so that the outer and inner circuit layers are thick, the top solder resist is thin, and the thickness of the bottom solder resist is between 5 ㎛ and 25 ㎛.

본 논문에서는 FEM(유한요소법)을 사용하여 PoP (Package on Package)용 PCB를 unit(유닛)과 substrate(서브스트레이트)로 분리한 warpage 해석과 warpage에 미치는 층별 두께의 영향도 분석과 층별 두께 조건을 다구찌법에 의한 SN비(Signal-to-Noise ratio)로 분석하였다. 해석 결과에 의하면 유닛 PCB는 회로층의 영향이 대단히 높았는데 특히 외층의 영향도가 높았다. 반면에 서브스트레이트 PCB는 회로층의 영향도가 높았으나 유닛 PCB에 비해 상대적으로 낮았으며 오히려 솔더 레지스트의 영향도가 증가하였다. 따라서 유닛 PCB와 서브스트레이트 PCB를 동시에 고려하여 PoP PCB의 층별 구조는 외부와 내부 회로층은 두껍게, 윗면 솔더 레지스트는 얇게 설계하고 바닥면 솔더 레지스트의 두께를 5 ㎛와 25 ㎛ 사이의 두께를 선정하는 바람직하다.

Keywords

Acknowledgement

이 연구는 한국연구재단 이공학 개인기초 연구사업(기본연구)의 지원(과제명: (201800050004)반도체 패키지용 PCB의 warpage 불량 감소 solution개발)으로 수행되었습니다.

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