• Journal of the Microelectronics and Packaging Society
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• v.9 no.2
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• pp.55-60
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• 2002

The recent trend in electronic devices has been towards light weight, low cost, high performance and improved reliability. Passive components are very important parts of microelectronic devices. The number of passive components used in hand held devices and computers continue to increase. To achieve improvements in costs, component density, performance, and reliability, embedding of these passive components into the printed circuit boards (PCBs) is required. This paper introduces the embedding of passive components, and discusses the remained challenges in the commercialization of this technique.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.151-155
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• 2003

The requirements for harsh environment electronic controllers in automotive applications have been steadily becoming more and more stringent. Electronic substrate technologists have been responding to this challenge effectively in an effort to meet the performance, reliability and cost requirements. An effect of the plasma cleaning at the alumina substrate and the IMC layer between $Sn-37wt\%Pb$ solder and Ag-Pd thick film conductor after reflow soldering has been studied. Organic residual carbon layer was removed by the substrate plasma cleaning. So the interfacial adhesive strength was enhanced. As a result of AFM measurement, Ag-Pd conductor pad roughness were increased from 304nm to 330nm. $Cu_6Sn_5$ formed during initial ref]ow process at the interface between TiWN/Cu UBM and solder grew by the succeeding reflow process so the grains had a large diameter and dense interval. A cellular-shaped $Ag_3Sn$ was observed at the interface between Ag-Pd conductor pad and solder. The diameters of the $Ag_3Sn$ grains ranged from about $0.1\~0.6{\mu}m$. And a needle-shaped $Ag_3Sn$ was also observed at the inside of the solder.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Journal of the Korea Safety Management & Science
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• v.15 no.1
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• pp.109-120
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• 2013

As information-oriented industry has been developed and electronic devices has come to be smaller, lighter, multifunctional, and high speed, the components used to the devices need to be much high density and should have find pattern due to high integration. Also, diverse reliability problems happen as user environment is getting harsher. For this reasons, establishing and securing products and components reliability comes to key factor in company's competitiveness. It makes accelerated test important to check product reliability in fast way. Out of fine pattern failure modes, failure of Electrochemical Migration(ECM) is kind of degradation of insulation resistance by electro-chemical reaction, which it comes to be accelerated by biased voltage in high temperature and high humidity environment. In this thesis, the accelerated life test for failure caused by ECM on fine pattern substrate, $20/20{\mu}m$ pattern width/space applied by Semi Additive Process, was performed, and through this test, the investigation of failure mechanism and the life-time prediction evaluation under actual user environment was implemented. The result of accelerated test has been compared and estimated with life distribution and life stress relatively by using Minitab software and its acceleration rate was also tested. Through estimated weibull distribution, B10 life has been estimated under 95% confidence level of failure data happened in each test conditions. And the life in actual usage environment has been predicted by using generalized Eyring model considering temperature and humidity by developing Arrhenius reaction rate theory, and acceleration factors by test conditions have been calculated.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.25-29
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• 2022

Recently, the importance of electronic packaging technology has been attracting attention, and heterogeneous integration technology in which chips are stacked out-of-plane direction is being applied to the electronic packaging field. The 2.5D integration circuit is a technology for stacking chips using an interposer including TSV, and is widely used already. Therefore, it is necessary to make the interposer mechanically reliable in the packaging process that undergoes various thermal processes and mechanical loadings. Considering the structural characteristics of the interposer on which several thin films are deposited, thermal stress due to the difference in thermal expansion coefficients of materials can have a great effect on reliability. In this study, the mechanical reliability of the metal pad for wire bonding on the silicon interposer against thermal stress was evaluated. After heating the interposer to the solder reflow temperature, the delamination of the metal pad that occurred during cooling was observed and the mechanism was investigated. In addition, it was confirmed that the high cooling rate and the defect caused by handling promote delamination of the metal pads.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.21-30
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• 2018

Driven by the recent energy saving trend, conventional silicon based power conversion modules are being replaced by modules using silicon carbide. Previous papers have focused mainly on the electrical advantages of silicon carbide semiconductors that can be used to design switching devices with much lower losses than conventional silicon based devices. However, no systematic study of their thermomechanical reliability in power conversion modules using finite element method (FEM) simulation has been presented. In this paper, silicon and silicon carbide based power devices with three-phase switching were designed and compared from the viewpoint of thermomechanical reliability. The switching loss of power conversion module was measured by the switching loss evaluation system and measured switching loss data was used for the thermal FEM simulation. Temperature and stress/strain distributions were analyzed. Finally, a thermal fatigue simulation was conducted to analyze the creep phenomenon of the joining materials. It was shown that at the working frequency of 20 kHz, the maximum temperature and stress of the power conversion module with SiC chips were reduced by 56% and 47%, respectively, compared with Si chips. In addition, the creep equivalent strain of joining material in SiC chip was reduced by 53% after thermal cycle, compared with the joining material in Si chip.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.37-42
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• 2003

In soldering of electronic packaging, the research on substituting lead-free solder materials for Pb-Sn alloys has become active due to environmental and health concerns over the use of lead. The reliability of the solder joint is very important in the development of solder materials and it is known that it is related to wettability of the solder over the substrate and microstructural evolution during soldering. It is also highly affected by type and extent of the interfacial reaction between solder and substrate and therefore, it is necessary to understand the interfacial reaction between solder and substrate completely. In order to predict the intermetallic compound (IMC) phase which forms first at the substrate/solder interface during the soldering process, a thermodynamic methodology has been suggested. The activation energy for the nucleation of each IMC phases is represented by a function of the interfacial energy and the driving force for phase formation. From this, it is predicted that the IMC phase with the smallest activation energy forms first. The grain morphology of the IMC at the solder joint is also explained by the calculations which use the energy. The Jackson parameter of the IMC grain with a rough surface is smaller than 2 but it is larger than 2 in the case of faceted grains.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.89-93
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• 2018

Ceramic substrates applied to power modules of electric vehicles are required to have properties of high thermal conductivity, high electrical insulation, low thermal expansion coefficient and resistance to abrupt temperature change due to high power applied by driving power. Aluminum nitride and silicon nitride, which are applied to heat dissipation, are considered as materials meeting their needs. Therefore, in this paper, the properties of aluminum nitride and silicon nitride as radiator plate materials were compared through a commercial analysis program. As a result, when the process of applying heat of the same condition to aluminum nitride was implemented by simulation, the silicon nitride exhibited superior impact resistance and stress resistance due to less stress and warping. In terms of thermal conductivity, aluminum nitride has superior properties as a heat dissipation material, but silicon nitride is more dominant in terms of reliability.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.351-357
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• 2005

Comparison of shear strength and shear energy of the 48Sn-52In solder bumps reflowed on Cu UBM were made with variations of reflow temperature from $150^{\circ}C$ to $250^{\circ}C$ and reflow time from 1 min to 20 min to establish an evaluation method for the mechanical reliability of solder bumps. Compared to the shear strength, the shear energy of the Sn-52In solder bumps was much more consistent with the solder reaction behavior and the fracture mode at the Sn-52In/Cu interface, indicating that the bump shear energy can be used as an effective tool to evaluate the mechanical integrity of solder/UBM interface.