• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.40-45
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• 1994

$112^{\circ}$ rot. x-cut $LiTaO_{3}$ wafer was used as the substrate of SAW gas sensor. Dual delay line SAW device with IDTs which consist of the reference delay line and the sensing delay line was fabricated using photolithigraphy. Each IDTs had 10 finger pairs and finger spacing is 10 microns. One delay line channel is the reference, while the second is the sensing channel with Pb-phthalocyanine film in the propagation path. Pb-phthalocyanine film which is p-type organic semiconductor was evaporated in $10^{-5}$ torr vacuum using shadow mask selectively. Dual delay line oscillator was constructed by using the rf amplifier and AGC. Frequency of the IDTs had the range of $87{\sim}$89 MHz oscillation frequency. Oscillation frequency shifts were investigated as a function of the temperature and the concentration of $NO_{2}$ gas.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.317-323
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• 1998

A synchronization is important element not only wire communication but also wireless communication. Especially, In SS(Spread Spectrum) communication method used GPS(Global Positioning System) synchronization is more important. A synchronous oscillator(SO) is a network which synchronizes, tracks, filter, amplifies and divides (if necessary) in a single process. Without an input signal, the SO is a free-running oscillator, oscillating at a frequency $w_0$, but phase changes $180^{\circ}$ within tracking range of SO. Therefore CPSO was used for this problem. The coherent phase synchronous oscillator(CPSO) is created by adding two external loops to the SO and has a wider tracking bandwidth and a zero-offset phase response (coherent) while maintaining the SO properties of high signal-to-rejection and fast frequency acquisition times. Therefore phase between input signal and output signal is synchronized. In this paper, GPS data recovery circuit has applied CPSO using front reference characters and has certified an excellent data recovery capability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.191-200
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• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Journal of electromagnetic engineering and science
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• v.17 no.3
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• Journal of the Korean Magnetics Society
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• v.14 no.4
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• pp.138-142
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• 2004

Uncertainty and characteristics of the developed current sensor by means of two identically wound magnetic cores forming a ring like for measurement of a low DC current such as leakage current was described in this paper. This transducer consists of a sensor type of a current transformer, peak value detectors, a reference alternating low frequency voltage oscillator, precision measuring circuits to measure the output signals of sensor with harmonics, and can be measured up to 2 A at DC current. The resolution and sensitivity of the sensor were 0.1㎃ and 10㎷/㎃, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• International Journal of Ocean System Engineering
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• v.1 no.4
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• pp.205-210
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• 2011

High data-rate underwater communications is demanded. This demand imposes stringent requirements on underwater communication equipment of phase-locked-loop (PLL). Phase noise in PLL is unwanted and unavoidable. In this paper, we investigate the PLL phase noise effect on high order QAM for underwater communication systems. The phase noise model using power spectral density is adopted for performance evaluation. The phase noise components considered in PLL are reference oscillator, voltage controlled oscillator (VCO), filter and divider. The filters in PLL noise are assumed to be second order active and passive low pass filters. Through simulation, we analyze the phase noise characteristics of the four components and then investigate the performance improvement factor of each component. Consequently, we derive specifications of VCO, phase detector, divider to meet performance requirement of high data-rate communication using QAM under phase noise influence.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of Advanced Navigation Technology
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• v.3 no.2
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• pp.120-131
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• 1999

For the phase measurement in the radar system using the magnetron pulse source, the STALO (Stable Local Oscillator) frequency need to be controlled to provide the stable intermediate frequency. In radar receiver, AFC(Automatic Frequency Control) circuit detects the transmitting frequency change and controls the STALO frequency to keep the intermediate frequency stable. In this paper, we designed and implimented AFC circuits for radar receiver. The frequency deviation is detected and compared with the reference frequency and the STALO frequency is controlled by the digital command signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.739-745
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• 1993

In mobile communication instruments, realization of the frequency synthesizer with high stabililty in temperature is very important. In order to realize a high stability frequency synthesizer, the oscillator providing for reference frequency must be stabilized in various temperature. In accordance to this requirement, the TCXO using digital method is rrealized in this thesis. The DTCXO consists of temperature sensing part, control part and the VCXO. The frequency stability of the realized DTCXO is 0.94 ppm on average. This is an improved result when compared with the 2.5 ppm of the TCXO using analog method.