• Korean Journal of Materials Research
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• v.5 no.1
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• pp.42-54
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• 1995

$Ta_2O_5$ thin film IS a promising material for the high dielectrics of ULSI DRAM. In this study, $Ta_2O_5$ thin film was grown on p-type( 100) Si wafer by thermal metal organic chemical vapo deposition ( MCCVD) method and the effect of operating varialbles including substrate temperature( $T_s$), bubbler temperature( $T_ \sigma$), reactor pressure( P ) was investigated in detail. $Ta_2O_5$ thin film were analyzed by SEM, XRD, XPS, FT-IR, AES, TEM and AFM. In addition, the effect of various anneal methods was examined and compared. Anneal methods were furnace annealing( FA) and rapid thermal annealing( RTA) in $N_{2}$ or $O_{2}$ ambients. Growth rate was evidently classified into two different regimes. : (1) surface reaction rate-limited reglme in the range of $T_s$=300 ~ $400 ^{\circ}C$ and (2: mass transport-limited regime in the range of $T_s$=400 ~ $450^{\circ}C$.It was found that the effective activation energies were 18.46kcal/mol and 1.9kcal/mol, respectively. As the bubbler temperature increases, the growth rate became maximum at $T_ \sigma$=$140^{\circ}C$. With increasing pressure, the growth rate became maximum at P=3torr but the refractive index which is close to the bulk value of 2.1 was obtained in the range of 0.1 ~ 1 torr. Good step coverage of 85. 71% was obtained at $T_s$=$400 ^{\circ}C$ and sticking coefficient was 0.06 by comparison with Monte Carlo simulation result. From the results of AES, FT-IR and E M , the degree of SiO, formation at the interface between Si and TazO, was larger in the order of FA-$O_{2}$ > RTA-$O_{2}$, FA-$N_{2}$ > RTA-$N_{2}$. However, the $N_{2}$ ambient annealing resulted in more severe Weficiency in the $Ta_2O_5$ thin film than the TEX>$O_{2}$ ambient.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.12 no.1
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• pp.62-68
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• 1999

Ferroelectric $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$(x=0, 0.1, 0.2, 0.3) thin films were deposited on $Pt/SiO_2/Si$ substrate by MOD(Metalorganic Decomposition) process. Metal carboxylate and metal alkoxide were used as precursors, and 2-methoxyethanol, xylene as solvents. After spin coating, thin films were pre-annealed at $400^{\circ}C$, followed by RTA(Rapid Thermal Annealing) and final annealing at $800^{\circ}C$ in oxygen atmosphere. These procedures were repeated three times to obtain thin films with the thickness of $2000{\AA}$. To enhance the nucleation and growth of layered-perovskite phase, thin films were rapid-thermally annealed above $720^{\circ}C$ in oxygen atmosphere. As RTA temperature increased, fluorite phase was transformed to layered-perovskite phase. And the change of Nb contents affected dielectric / electrical properties and microstructure. The ferroelectric characteristics of $Sr_{0.7}/B_{2.3}(Ta_{1-x}Nb_x)_2O_9$ thin film were Pr=8.67 $\mu{C}/cm^2$, Ec=62.4kV/cm and $I_{L}=1.4\times10^{-7}A/cm^2$ at the applied voltage of 5V, respectively.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.81-90
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• 1990

In this study, ion beam deposited tungsten thin film for gate material of GaAs SAGFET(Self Aligned Gate FET) was annealed from 800\ulcorner to 900\ulcorner using RTA and detailed investigations of structural and electrical characteristics of this film were carried out using four-point probe, XRD, SEM, AES and current-voltage measurement. Investigated results showed phase of as deposited tungsten film was fine grain \ulcornerphase and phase tdransformation of this film into \ulcornerphase occured at annealing condition of 900\ulcorner, 6sec. But regardless of phase transformation, electrical characteristics of tungsten film were very stable to 900\ulcorner and in case of 900\ulcorner, 4sec annealing condition Schottky barrier height obtained from 10 diodes measurements was 0.66 + 0.003 eV.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1477-1479
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• 2000

The annealing treatments on rf magnetron sputtered PZT($Pb_{1.05}(Zr_{0.52},Ti_{0.48})O_3$) thin films(4000${\AA}$) have been investigated for a structure of PZT/Pt/Ti/ITO coated glass. Crystallization properties of PZT films were strongly dependent on RTA(Rapid Thermal Annealing) annealing temperature and time. We were able to obtain a perovskite structure of PZT at 650$^{\circ}C$ and 10min. P-E curves of Pd/PZT/Pt capacitor demonstrate typical hysteresis loops. The measured values of $P_r$, $E_c$ were 15.8[${\mu}C/cm^2$], 95[kV/cm] respectively. Polarization value decrease about 10% after $10^9$ cycles.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.213-219
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• 1992

The microstructure, dopant distribution and electrical properties of the $As^{+}$ ion-implanted surface layer differ significantly depending on the methods of subsequent heat treatments, furnace annealing(FA) and rapid thermal annealing(RTA). The amorphous layer created by ion implantation was recrystallized during the thermal annealing through solid phase epitaxial (SPE) growth. The dopant distribution and electrical properties are discussed with respect to the TEM cross-sectional microstructure observed. The microstructure, dopant distribution and electrical properties depended upon especially the annealing time of the heat treatment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.3
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• pp.237-241
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• 1998

In this study, PLZT stock solutions around x/65/35 (x=6~11) ferroelectric region were prepared by Sol-Gel method and deposited on ITO-glass by spin-coating method. The thin films were annealed by RTA(rapid thermal annealing). The variations of crystallographic structure of the thin films were observed using XRD and hysteresis curves, dielectric characteristics, and optical transmittances were measured in order to investigate the characteristics of the thin films. The thin films were crystallized at $750^{\circ}C$ for 5 min by RTA. Relative dielectric constant and optical transmittance increased with increasing La content, Ec and Pr were higher for thin films than for bulk materials.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.139-142
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• 2002

Characteristics of piezoelectric thick films prepared by screen printing were investigated. The piezoelectric thick films were fabricated using Pb(Al,Nb)O$_3$-Pb(Zr,Ti)O$_3$ system on Si-substrate. The fabricated thick films were burned out at 400$^{\circ}C$ and sintered at 850∼1000$^{\circ}C$ using rapid thermal annealing(RTA) precess. The thickness of piezoelectric thick films were 10$\mu\textrm{m}$. PAN-PZT thick film on Ag-Pd/SiO$_2$/Si prepared at 900$^{\circ}C$/1300sec had remanent polarization of 19.70 ${\mu}$C/$\textrm{cm}^2$.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.647-653
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• 1988

A rapid thermal annealing system using tungsten halogen lamp has been designed and assembled. A control scheme where the temperature control is executed with calculated wafer temperature by considering the thermocouple delay rather than measured thermocouple temperature,is proposed. This control scheme gives more accurate control of the wafer temperature. In addition, the distribution of transmitted light power to the wafer in the system has been simulated, and lamp interval modification has been able to give more uniform light power distribution. Considering incident light spectrum, absorption, reflection, radiation of silicon, etc., temperature profile has been simulated. When the light power uniformity on the 3" wafer is below 1%, the temperature uniformity is about 2%.