• Title/Summary/Keyword: RSA 알고리즘

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Key Recovery Algorithm from Randomly-Given Bits of Multi-Prime RSA and Prime Power RSA (비트 일부로부터 Multi-Prime RSA와 Prime Power RSA의 개인키를 복구하는 알고리즘)

  • Baek, Yoo-Jin
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.6
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    • pp.1401-1411
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    • 2016
  • The Multi-Prime RSA and the Prime Power RSA are the variants of the RSA cryptosystem, where the Multi-Prime RSA uses the modulus $N=p_1p_2{\cdots}p_r$ for distinct primes $p_1,p_2,{\cdots},p_r$ (r>2) and the Prime Power RSA uses the modulus $N=p^rq$ for two distinct primes p, q and a positive integer r(>1). This paper analyzes the security of these systems by using the technique given by Heninger and Shacham. More specifically, this paper shows that if the $2-2^{1/r}$ random portion of bits of $p_1,p_2,{\cdots},p_r$ is given, then $N=p_1p_2{\cdots}p_r$ can be factorized in the expected polynomial time and if the $2-{\sqrt{2}}$ random fraction of bits of p, q is given, then $N=p^rq$ can be factorized in the expected polynomial time. The analysis is then validated with experimental results for $N=p_1p_2p_3$, $N=p^2q$ and $N=p^3q$.

Scalable RSA public-key cryptography processor based on CIOS Montgomery modular multiplication Algorithm (CIOS 몽고메리 모듈러 곱셈 알고리즘 기반 Scalable RSA 공개키 암호 프로세서)

  • Cho, Wook-Lae;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.1
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    • pp.100-108
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    • 2018
  • This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

Encryption of Biometrics data for Security Improvement in the User Authentication System (사용자 인증 시스템의 보안성 향상을 위한 생체인식 데이터의 암호화)

  • Park, Woo-Geun
    • Journal of IKEEE
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    • v.9 no.1 s.16
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    • pp.31-39
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    • 2005
  • This paper presented new biometrics data transfer model, and use MD5 (Message Digest5) and RSA (Ron Rivest, Adi Shamir, Len Adleman) algorithm to improve biometrics data's security. So, did so that can run user authentication more safely. That is, do so that may input fingerprint among biometrics through client, and transmit processed fingerprint to server. When fingerprint information is transmitted, it uses MD5 algorithm to solve problem that get seized unlawful living body information from outside and information does Digest. And did to pass through process that transmit again this by RSA method. Also, experimented general text data and living body data that is not encoded, transmission speed and security of living body data that encoding and transmit each comparison. By running user authentication through such improved method, is expected to be applied in several. fields by method to simplify certification procedure and is little more correct and stable.

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Implementation of High-radix Modular Exponentiator for RSA using CRT (CRT를 이용한 하이래딕스 RSA 모듈로 멱승 처리기의 구현)

  • 이석용;김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.10 no.4
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    • pp.81-93
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    • 2000
  • In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

Performance Comparison of the CELM Encryption Algorithm (CELM 암호화 알고리즘의 성능 비교)

  • 박혜련;이종혁
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.3
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    • pp.481-486
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    • 2002
  • In this paper, we propose CELM(Cascade ELM) to improve stability. We could realize as cascade connected each other key value with N degree equation which has a initial value. And we could know to be improved in stability with the nature of Chaos in simulation result. In efficiency, this CELM algorithm identified sire of encrypted code with size of source code and we could know more efficient than existing RSA and ECC. In speed, CELM took average 0.18㎳ degree to encrypt a file. Although it was slower than DES, it was faster than ECC of RSA.

양자컴퓨터를 통한 대칭키 및 공개키 해킹 동향

  • Yujin Oh;Yujin Yang;Kyungbae Jang;Hwa-jeong Seo
    • Review of KIISC
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    • v.33 no.2
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    • pp.13-20
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    • 2023
  • 양자 알고리즘이 구동 가능한 양자 컴퓨터는 현대 암호들이 기반하고 있는 수학적 난제들을 빠르게 해결할 수 있다, 대칭키 암호의 경우, Grover 알고리즘을 사용한 전수조사 가속화가 가능하며, 공개키 암호의 경우, Shor 알고리즘을 사용하여 RSA와 ECC가 기반하고 있는 난제들을 다항시간 내에 해결할 수 있다. 이에 다양한 대칭키 암호, 그리고 RSA와 ECC의 양자 해킹 방법론에 대한 연구들이 수행되고 있다. 물론 양자컴퓨터의 제한적인 성능으로 인해 실제 해킹이 가능한 수준은 아니지만, 양자 공격 회로를 제시하고 그에 필요한 양자 자원들을 분석하는 방식으로 실제 해킹 가능성에 대해 추정해 보는 연구 결과들이 발표되고 있다. 이에 본 기고에서는 양자 컴퓨터를 통한 대칭키 및 공개키 암호 해킹 동향에 대해 살펴보고자 한다.

A Study on the Modulus Multiplier Speed-up Throughput in the RSA Cryptosystem (RSA 암호시스템의 모듈러 승산기 처리속도 향상을 위한 연구)

  • Lee, Seon-Keun;Jeung, Woo-Yeol
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.3
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    • pp.217-223
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    • 2009
  • Recently, the development of the various network method can generate serious social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security field such as hacking, cracking. The way to preserve security from hacker or cracker without developing new cryptographic algorithm is keeping the state of anti-cryptanalysis in a prescribed time by means of extending key-length. In this paper, the proposed montgomery multiplication structured unit array method in carry generated part and variable length multiplication for eliminating bottle neck effect with the RSA cryptosystem. Therefore, this proposed montgomery multiplier enforce the real time processing and prevent outer cracking.

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Reverse Baby-step 2k-ary Adult-step Method for 𝜙((n) Decryption of Asymmetric-key RSA (비대칭키 RSA의 𝜙(n) 해독을 위한 역 아기걸음- 2k-ary 성인걸음법)

  • Lee, Sang-Un
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.6
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    • pp.25-31
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    • 2014
  • When the public key e and the composite number n=pq are disclosed but not the private key d in an asymmetric-key RSA, message decryption is carried out by obtaining ${\phi}(n)=(p-1)(q-1)=n+1-(p+q)$ and subsequently computing $d=e^{-1}(mod{\phi}(n))$. The most commonly used decryption algorithm is integer factorization of n/p=q or $a^2{\equiv}b^2$(mod n), a=(p+q)/2, b=(q-p)/2. But many of the RSA numbers remain unfactorable. This paper therefore applies baby-step giant-step discrete logarithm and $2^k$-ary modular exponentiation to directly obtain ${\phi}(n)$. The proposed algorithm performs a reverse baby-step and $2^k$-ary adult-step. As a results, it reduces the execution time of basic adult-step to $1/2^k$ times and the memory $m={\lceil}\sqrt{n}{\rceil}$ to l, $a^l$ > n, hence obtaining ${\phi}(n)$ by executing within l times.

Secure Scalar Multiplication with Simultaneous Inversion Algorithm in Hyperelliptic Curve Cryptosystem (초 타원 곡선 암호시스템에서 동시 역원 알고리즘을 가진 안전한 스칼라 곱셈)

  • Park, Taek-Jin
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.4 no.4
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    • pp.318-326
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    • 2011
  • Public key cryptosystem applications are very difficult in Ubiquitos environments due to computational complexity, memory and power constrains. HECC offers the same of levels of security with much shorter bit-lengths than RSA or ECC. Scalar multiplication is the core operation in HECC. T.Lange proposed inverse free scalar multiplication on genus 2 HECC. However, further coordinate must be access to SCA and need more storage space. This paper developed secure scalar multiplication algorithm with simultaneous inversion algorithm in HECC. To improve the over all performance and security, the proposed algorithm adopt the comparable technique of the simultaneous inversion algorithm. The proposed algorithm is resistant to DPA and SPA.