• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1452-1453
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• 2008

본 논문에서는 RF MEMS 패키징 플랫폼을 활용한 안테나 구조를 제안하고, 이를 바탕으로 마이크로머시닝 공정을 이용한 슬롯 결합형 원형 패치 안테나를 제작하였다. 제안된 안테나는 RF MEMS 패키징 플랫폼 상에서 패키징 물질을 안테나의 유전 물질로 이용하기 위하여 슬롯 결합형 급전 구조를 사용하였다. 한편, BCB를 이용한 폴리머 접착 접합 공정의 RF MEMS 패키징 플랫폼을 기반으로, 하판 유리기판과 상판 수정 기판을 일체화한 형태로 마이크로 스트립라인 안테나를 제작하였다. 최종 제작된 안테나는 20.36-GHz에서 -21 dB의 반사 손실 값을 나타내며, 1.7-GHz, 즉 8.3 %의 주파수 대역을 가진다.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.124-128
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• 2001

We apply for the first time a low cost and loss wafer level packaging technology for RF-MEMS device. The proposed structure was simulated by finite element method (FEM) tool (HFSS of Ansoft). S-parameter measured of the package shows the return loss (S11) of 20dB and the insertion loss (S21) of 0.05dB.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1511_1512
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• 2009

This paper presents a polarization switching antenna integrated with silicon RF MEMS SPDT switches in the form of a package. A low-loss quartz substrate made of SoQ (silicon-on-quartz) bonding is used as a dielectric material of the patch antenna, as well as a packaging lid substrate of RF MEMS switches. The packaging/antenna substrate is bonded with the bottom substrate including feeding lines and RF MEMS switches by BCB adhesive bonding, and RF energy is transmitted from signal lines to antenna by slot coupling. Through this approach, fabrication complexity and degradation of RF performances of the antenna due to the parasitic effects, which are all caused from the packaging methods, can be reduced. This structure is expected to be used as a platform for reconfigurable antennas with RF MEMS tunable components. A linear polarization switching antenna operating at 19 GHz is manufactured based on the proposed method, and the fabrication process is carefully described. The s-parameters of the fabricated antenna at each state are measured to evaluate the antenna performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.11-15
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• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.