• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.30-33
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• 1999

본 연구에서는 Pt/f4-SiC Schottky barrier diodes(SBDs)의 소자 성능향상과 미세구조와의 상관관계를 규명하였다. 다른 열처리 온도구간에 따른 금속/SiC 계면의 미세구조 평가는 X-ray scattering법을 사용하여 분석하였다. 소자의 역 방향 특성은 열처리 온도가 증가함에 따라 저하되었다. As-deposited와 $850^{\circ}C$ 온도에서 열처리된 소자의 최대 항복전압은 각각 1300 V와 626 V 이었다. 그러나, 소자의 순방향 특성은 열처리 온도가 증가함에 따라 향상되었다. X-ray scattering법으로 >$650^{\circ}C$ 이상의 열처리 온도에서는 Pt/SiC 계면에서 Pt-silicides가 형성되었고, 이러한 Silicides의 형성이 Pt/SiC 계면의 평활도를 증가시킨 원인이 됨을 보였다. SBDs의 순방향 특성은 열처리 과정동안 Pt/SiC 계면에서 형성된 silicides의 결정성에 강하게 의존함을 알 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.149.1-149.1
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• 2013

Noble metal silicides are widely used in silicon based microelectronic and optoelectronic devices. Among them, as compared to other silicides, structural and electronic properties of platinum silicide (PtSi) are found to be less sensitive to change in its dimensions. PtSi is known to overcome the junction spiking problems of Al-Si contacts. Present study is regarding the spatial evolution of platinum silicide in Pt/SiOx/Si. Scanning photoelectron emission microscopy (SPEM) was used for this purpose. SPEM images were obtained for pristine samples and after an annealing at $500^{\circ}C$ for 1 hr. Core-level spectra were recorded at different points in SPEM images contrasted by the intensity of Pt 4f7/2. Both Pt 4f and Si 2p spectra reveal the formation of PtSi after annealing. However, in contrast to earlier reports, PtSi formation is found to be non-uniform confirmed by the SPEM images and from the core level spectra taken at different intensity points.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.343-343
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• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.64-65
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• 1993

MPB 조성영역인 Zr/Ti=52/48의 composite ceramic target을 사용하여 RF magnetron sputtering 방법으로 기판온도 약 30$0^{\circ}C$에서 RZT 박막을 Pt/Ti/Si 기판위에 증착시켰다. 안정상인 perovskite 구조를 형성시키기 위하여 PbO분위기에서 furnace annealing 과 Repid thermal annealing을 실시하여 열처리 방법에 따른 상형성 및 계면반응과 그에 따른 전기적 특성을 고찰 하였다. Pt 의 두께가 250$\AA$인 경우 furnace annealing 시 $650^{\circ}C$에서 perouskite 상이 형성되었으나 Pt층이 산소의 확산을 방지하지 못하여 상부의 Ti 층이 TiOx로 변태하였으며 하부의 Ti는 Si 과 반응하여 Ti-silicide 롤 변태하였다. 또한 75$0^{\circ}C$,60sec 인 경우 Pt 층의 응집화가 관찰되어 하부전극으로서 적용이 적절하지 못하다. 급속열처리를 실시한 경우에도 마찬가지로 Ti 층이 TiOx 와 silicide 층으로 변태되었다. Pt의 두께가 1000$\AA$인 경우에도 250$\AA$와는 달리 RTA 시 (III)방향으로 Furace annealing 시(001)방향으로 우선 성장하였다. 이는 Ti(001), P(111),PZT(111)면의 lattic mismatch 가 매우 작은데다 RTA 시 계면반응이 거의발생하지 않아 PZT 박막이 (111) 방향으로 우선 성장한 것으로 보인다. Furnace annealing 경우는 심한 계면반응이 발생하여 Pt층에 어느 정도 영향을 주었기 때문에 우선성장 방향이 바뀌었다구 생각한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.353-353
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• 2010

본 논문에서는 소스와 드레인의 형성에 있어서 implantation 이 아닌 silicide를 형성시켜서 최고온도 $500^{\circ}C$가 넘지않는 저온공정을 실현하였고, silicon-on-insulator (SOI) 기판이 아닌 solid phase crystallization (SPC) 결정화 방법을 이용하여 결정화 시킨 SPC-TFT 기판을 사용하였다. Silicide 의 형성은 pt를 증착하여 furnace에서 열처리를 실시하여 형성하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.36-36
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• 2009

In this work, we describe a method to fabricate the Pt-silicided SB-MOSFETs with a n-type Silicon-On-Insulator (SOI) substrate as an active layer and demonstrate their electrical and structural properties. The fabricated SB-MOSFETs have novel structure and metal gate without sidewall. The gate oxide with a thickness of 7 nm was deposited by sputtering. Also, this fabrication processes were carried out below $500^{\circ}C$. As a result, Subthreshold swing value and on/off ratio of Fabricated SB MOSFETs was 70 [mV/dec] and $10^8$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.4
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• pp.1-7
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• 2017

Cobalt silicide was used as a counter electrode in order to confirm its reliability in dye-sensitized solar cell (DSSC) devices. 100 nm-Co/300 nm-Si/quartz was formed by an evaporator and cobalt silicide was formed by vacuum heat treatment at $700^{\circ}C$ for 60 min to form approximately 350 nm-CoSi. This process was followed by etching in $80^{\circ}C$-30% $H_2SO_4$ to remove the cobalt residue on the cobalt silicide surface. Also, for the comparison against Pt, we prepared a 100 nm-Pt/glass counter electrode. Cobalt silicide was used for the counter electrode in order to confirm its reliability in DSSC devices and maintained for 0, 168, 336, 504, 672, and 840 hours at $80^{\circ}C$. The photovoltaic properties of the DSSCs employing cobalt silicide were confirmed by using a simulator and potentiostat. Cyclic-voltammetry, field emission scanning electron microscopy, focused ion beam scanning electron microscopy, and energy dispersive spectrometry analyses were used to confirm the catalytic activity, microstructure, and composition, respectively. The energy conversion efficiency (ECE) as a function of time and ECE of the DSSC with Pt and CoSi counter electrodes were maintained for 504 hours. However, after 672 hours, the ECEs decreased to a half of their initial values. The results of the catalytic activity analysis showed that the catalytic activities of the Pt and CoSi counter electrodes decreased to 64% and 57% of their initial values, respectively(after 840 hours). The microstructure analysis showed that the CoSi layer improved the durability in the electrolyte, but because the stress concentrates on the contact surface between the lower quartz substrate and the CoSi layer, cracks are formed locally and flaking occurs. Thus, deterioration occurs due to the residual stress built up during the silicidation of the CoSi counter electrode, so it is necessary to take measures against these residual stresses, in order to ensure the reliability of the electrode.

• Proceedings of the Korean Vacuum Society Conference
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• 2004.02a
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• pp.52-52
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• 2004

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.53-59
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• 2003

Using Platinum-silicide (PtSi) formed between silicon substrate and carbon film, we have improved the field emission of electrons from carbon films. Pt films were deposited on n-Si(100) substrates at room temperature by DC sputter technique. After deposition, these PtSi thin films were annealed at 400 ~ $600^{\circ}C$ in a vacuum chamber, and the carbon films were deposited on those Pt/Si substrates by laser ablation at room temperature. The field emission property of C/Pt/Si system is found to be better than that of C/Si system and it is showed that property was improved with increasing annealing temperature. The reasons why the field emission from carbon film was improved can be considered as follows, (1)the resistance of carbon films was decreased due to graphitization, (2)electric field concentration effectively occurred because the surface morphology of carbon film deposited on Pt/si substrates with rough surface, (3)it is showed that annealing induced reaction between Pt film and Si substrate, as a consequence that the interfacial resistance between Pt film and Si substrate was decreased.