• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.35-43
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• 2008

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.415.2-415.2
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• 2016

Triboelectric nanogenerator (TENG) is one of ways to convert mechanical energy sound, waves, wind, vibrations, and human motions to available electrical energy. The principal mechanism to generate electrical energy is based on contact electrification on material surface and electrostatic induction between electrodes. The performance of TENG are dependent on amount of the input mechanical energy and characteristics of triboelectric materials. Furthermore, the whole TENG system including mechanical structure and electrical system can effect on output performance of TENG. In this work, we investigated the effect of gear train on output performance and power conversion efficiency (PCE) of TENG under a given input energy. We applied the gear train on mechanical structure to improve the contact rate. We measured the output energy under a constant input energy by controlling the size of the working gear. We prepared gears with gear ratios (rin/rw) of 1, 1.7, and 5. Under the constant input energy, the voltage and current from our gear-based TENG system were enhanced up to the maximum of 3.6 times and 4.4 times, respectively. Also, the PCE was increased up to 7 times at input frequency of 1.5 Hz. In order to understand the effect of kinematic design on TENG system, we performed a capacitor experiment with rectification circuit that provide DC voltage and current. Under the input frequency of 4.5 Hz, we obtained a 3 times enhanced rectifying voltage at a gear ratio of 5. The measured capacitor voltage was enhanced up to about 8 fold in using our TENG system. It is attributed that our gear-based TENG system could improve simultaneously the magnitude as well as the generation time of output power, finally enhancing output energy. Therefore, our gear-based TENG system provided an effective way to enhance the PCE of TENGs operating at a given input energy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.597-604
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• 2006

An ultrawideband(UWB) $3.1{\sim}5.15$ GHz low-noise amplifier employing a novel input matching circuit and feedback topology are presented. The proposed UWB amplifier is Implemented in $0.18{\mu}m$ RF CMOS technology. Measurements show a NF of $3.4{\sim}3.9$ dB, a power gain of $12.8{\sim}14$ dB, better than -9.4 of input matching and, an input IP3 of -1 dBm, while comsuming only 14.5 mW of power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Journal of Advanced Navigation Technology
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• v.19 no.3
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• pp.237-243
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• 2015

This paper presented the design of wireless power transfer (WPT) system using electromagnetic induction techniques and analysed WPT efficiency. Also, we presented the optimum coil condition by measuring the efficiency variation according to some receiving coil parameter changes. Voltage change is measured by receiving coil position for the designed transmitting and receiving circuit. Voltage change according to inductance variation at the same position and charging time are compared at the same environment by using a developed application program to realize an optimum WPT system. Developed wireless power transfer system using electromagnetic induction techniques uses 125 kHz. It takes 16 minutes by using wired charger, and 23 minutes by using wireless charger for charging from 50% to 60% charging status.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.408-414
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• 2005

The VCDRO(Voltage Controlled Dielectric Resonate. Oscillator) with low phase noise is designed using nonlinear analysis, and its phase noise characteristics are compared with that of Lesson's equation. The microstripline coupled with dielectric resonator is realized as a high impedance inverter to improve the phase noise performance, and the quality factor of resonator circuit can be transferred to active device with the enhanced the loaded quality factor. The worst case and part stress analyses are achieved to obtain the high reliability of VCDRO and the reliability analysis is accomplished to estimate the probability of operation at the end of life. The developed VCDRO has the oscillating tuning factor of 0.56MHZ1V for the control voltage range of 0-l2V. This VCDRO requires the DC power of 136mW. The phase noise characteristics exhibit good performances of -94.18dBc/Hz (a)10KHz and -116.3dBc/Hz (a)100KHz. And, the output power over 7.33dBm is measured.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.262-267
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• 2005

During several method of improvement efficient, We analyzed Doherty Amplifier That used by simple circuit and 180w PEP LDMOS to analyze improvement of efficient and linearity. We for testing performance of Doherty Amplifier compared with Balanced Class AB, the experimental results show when Peaking Amp $V_gs.P$=1.53V, the efficiency is increased at Maximum 11.6$\%$. After finding optimum bias point of linearity improvement by manual tuning gate bias, when WCDMA 4FA $V_gs.P$=3.68V IMSR could be increased maximum 3.34dB. especially, when we match bias point of Peaking amp at 1.53V, we could get a excellent efficiency increase and have fUR under -3203c at output power 43dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].