• 전자공학회논문지SC
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• 제46권4호
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• pp.64-69
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• 2009

본 논문은 모바일 디스플레이모듈의 signal integrity와 power integrity의 시뮬레이션 방법에 관한 것이다. 본 제안 방법은 커넥터, FPCB, 드라이버IC를 포함하는 회로모듈 해석에 사용할 수 있다. 최근에 모바일 디스플레이 업계의 시리얼 인터커넥션기술에 대한 필요성 대두로 시스템오동작 방지 및 전자기파 발생을 억제하기 위해 신호선과 전원전압에 대한 섬세한 컨트롤이 필요하다. S파라미터와 Z파라미터 분석으로 주파수 도메인과 시간 도메인에서의 상관관계를 분석한다. 멀티포트 매크로를 이용하여 시간 도메인에서 sigh integrity를 power integrity에 함께 분석할 수 있다.

• 한국항공우주학회지
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• 제48권1호
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• pp.63-72
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• 2020

본 연구에서는 위성용 전장품 보드의 성능 요구조건과 설계 복잡도가 높아지면서 증가되는 노이즈 문제를 최소화하기 위해 전원 건전성(Power Integrity) 및 신호 건전성(Signal Integrity)의 설계 분석이 수행되었고 이를 통해 적용된 설계 개선 내용을 기술하였다. 전원 건전성은 정전류 전압강하(DC IR drop) 해석을 통해 정적 전원의 특성을 분석하였고, 각 전원의 임피던스 해석을 통해 동적 전원의 특성을 분석하여 각 분석 결과를 이용한 설계 개선 방안들이 적용되었다. 신호 건전성 측면에서는 주요 데이터버스 신호에 대한 시간영역 파형 분석과 PCB(Printed Circuit Board) 설계 수정을 통해 노이즈가 개선된 결과를 확인하였다. 또한 설계된 PCB 보드의 전원 층에 대한 공진모드를 분석하여 발생된 공진 영역들에 완화 조치를 적용하였고 조치결과를 시뮬레이션을 통해 확인하였다. 최종적으로 분석을 통해 설계 개선이 적용된 유닛에 대해 수정 전과 후의 EMC(Electro Magnetic Compatibility) RE(Radiated Emission) 노이즈 측정결과를 비교함으로써 방사성 노이즈가 감소되었음을 확인하였다.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.3-14
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• 2013

In this paper, key design issues and considerations for Signal Integrity(SI) and Power Integrity(PI) of a TSV-based 3D IC are introduced. For the signal integrity and power integrity of a TSV-based 3-D IC channel, analytical modeling and analysis results of a TSV-based 3-D channel and power delivery network (PDN) are presented. In addition, various design techniques and solutions which are to improve the electrical performance of a 3-D IC are investigated.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2008년도 제7회 추계학술대회 및 정기총회
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• pp.391-394
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• 2008

• ETRI Journal
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• 제41권5호
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Journal of electromagnetic engineering and science
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• 제5권4호
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• pp.193-196
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• 2005

The DC power-bus for the PCB is loaded with metal walls on its selected sides and is characterized electromagnetically. This is a novel concept of approach to mitigate the spurious resonance and finally signal integrity problems. In particular, the peak at DC, which is always in the way to secure parallel-plates' EMC, can be completely removed by the proposed method. Through the findings of this study, the effect of metal-loading of the power-bus will be presented along with the impression that the suggested technique can tackle the headaches of signal integrity, ground bounce, EMIs.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.35-50
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• 2013

This paper discusses effects of mesh planes on signal integrity in high-speed glass ceramic packages. One of serious signal integrity issues in high-speed glass ceramic packages is high far-end (FE) noise coupling between signal interconnects. Based on signal integrity analysis, a methodology is presented for reducing far-end noise coupling between signal interconnects in high-speed glass ceramic modules. This methodology employing power/ground mesh planes with alternating spacing and a via-connected coplanar-type shield (VCS) structure is suggested to minimize far-end noise coupling between signal lines in high-speed glass ceramic packages. Optimized interconnect structure based on this methodology has demonstrated that the saturated far-end noise coupling of a typical interconnect structure in glass ceramic modules could be reduced significantly by 73.3 %.

• 한국정보전자통신기술학회논문지
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• 제14권6호
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• pp.452-460
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• 2021

전 세계적으로 전기차 시장이 확대됨에 따라 성능 및 안전성의 문제를 보완한 친환경적인 전기차가 계속 출시되고 시장이 더욱 커지고 있다. 하지만 전기차의 경우 충전의 불편함, 감전과 같은 안전 문제, 여러 전장부품들의 연동으로 인한 EMI(Electromagnetic interference) 문제는 전기차에서 해결해야 하는 문제이다. 무선전력전송 기술을 이용하면 전기차 충전에 대한 불편함 해소와 고전류, 고전압을 직접 다루지 않아 안전성의 문제를 해결할 수 있으나 EMI 저감을 위한 설계가 이루어지지 않는다면 오작동을 일으켜 더 큰 문제를 일으킬 수 있다. 본 논문은 전기차 무선전력전송 핵심 전장 부품인 무선충전컨트롤모듈에서 발생할 수 있는 EMI를 저감시키기 위한 전원무결성과 신호무결성을 갖는 전기차 무선전력전송 무선충전컨트롤모듈 EMI 저감 설계하였다. 전원부분에서 발생할 수 있는 공진, 임피던스 등의 문제와 신호 부분에서 발생할 수 있는 고속통신간의 신호왜곡의 문제를 시뮬레이션을 통해 EMI 저감 설계하였다.따라서 전원무결성과 신호무결성을 갖는 EMI 저감 설계를 통해 전기차 무선전력전송 무선충전컨트롤모듈 800 MHz ~ 1 GHz 대역과 1.5 GHz에서 각각 10 dBu V/m, 15 dBu V/m이 저감되는 것을 확인하였다.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권3호
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• pp.248-251
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• 2014

As more vehicles become equipped with advanced electronic control systems, more consideration is needed with regards to automotive safety issues related to the effects of electromagnetic waves. Unwanted electromagnetic waves from the antenna, electricity and other electronic devices cause the performance and safety problem of automotive components. In general, Power Integrity and Signal Integrity analysis have been widely used, but these analyses have stayed PCB level. PCB base analysis is different from radiated emission TEST condition so its results are used just for reference. This paper proposes EMC optimization technology using module level 3-dimensional radiation simulation process closed to fundamental test conditions. If module level EMC analysis, which is proposed in this study, is applied to all automotive electronics systems, unexpected EMC noise will be prevented.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.