Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

Analysis Method of Signal Integrity for Mobile Display Circuit Modules

모바일 디스플레이 회로 모듈의 시그널 인티그리티 해석 기법

  • Lee, Yong-Min (Dept. of Information Display, Sun Moon University)
  • 이용민 (선문대학교 정보디스플레이학과)
  • Published : 2009.07.25
Download PDF
⟨ Previous Next ⟩

Abstract

This paper addresses the simulation methodology of signal integrity and power integrity for mobile display modules. The proposed technique can be applied to analyse a circuit module which consist of connector, FPCB and driver ICs. The recent demand of serial interconnection technology in the mobile display industry needs delicate impedance control of signal and power traces to prohibit system malfunctioning and to reduce electromagnetic field radiation. Based on the S-parameter and Z-parameter analysis, we analyse the correlation between frequency-domain and time-domain measurements. With multi-port macros, signal integrity can be included in power integrity analysis in time domain.

본 논문은 모바일 디스플레이모듈의 signal integrity와 power integrity의 시뮬레이션 방법에 관한 것이다. 본 제안 방법은 커넥터, FPCB, 드라이버IC를 포함하는 회로모듈 해석에 사용할 수 있다. 최근에 모바일 디스플레이 업계의 시리얼 인터커넥션기술에 대한 필요성 대두로 시스템오동작 방지 및 전자기파 발생을 억제하기 위해 신호선과 전원전압에 대한 섬세한 컨트롤이 필요하다. S파라미터와 Z파라미터 분석으로 주파수 도메인과 시간 도메인에서의 상관관계를 분석한다. 멀티포트 매크로를 이용하여 시간 도메인에서 sigh integrity를 power integrity에 함께 분석할 수 있다.

Keywords

References

  1. Grivet-Talocia, F. Canavero, S. Acquadro, C. Peraldo, M. Rouvala, I. Kelander, 'Parametric Macromodeling of Flexible Printed Interconnects for Mobile Devices,' International Symposium on Electromagnetic Compatibility, pp. 851-856, Barcelona, Spain, September 2006
  2. Grivet-Talocia, S. Acquadro, M. Bandinu, F.G. Canavero, I. Kelander, M. Rouvala, 'Signal Integrity constrained optimization of flexible printed interconnects for mobile devices,' IEEE International Symposium on EMC, Portland, USA, August 2006 https://doi.org/10.1109/ISEMC.2006.1706388
  3. K.Y. See, M. Oswal, W. Khan-ngern, F. Canavero, C. Christopoulos, H. Grabinski, 'Impact of PCB Layout Design on Final Product's EMI Compliance,' 17th International Zurich Symposium on Electromagnetic Compatibility, pp. 553-556, Singapore, February 2006 https://doi.org/10.1109/EMCZUR.2006.214994
  4. I.S.Stievano, F.G.Canavero, I.A.Maio, 'Behavioral Macromodels of Digital IC Receivers for Analog-Mixed Signal Simulations,' IEE Electronics Letters, Vol. 41, No. 7, March 2005 https://doi.org/10.1049/el:20058186
  5. Grivet-Talocia, 'Delay-Based Macromodels for Long Interconnects via Time-Frequency Decomposition,' IEEE 15th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 199-202, Scottsdale, USA, October 2006 https://doi.org/10.1109/EPEP.2006.321228
  6. A. Vaidyanath, B. Thorodden and J. L. Prince, 'Effect of CMOS Driver Loading Conditions on Simultaneous Switching Noise,' IEEE Trans. CPMT-PART B. vol.17, No.4, pp. 480-485, November, 1994 https://doi.org/10.1109/96.338712