• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.64-69
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• 2009

This paper addresses the simulation methodology of signal integrity and power integrity for mobile display modules. The proposed technique can be applied to analyse a circuit module which consist of connector, FPCB and driver ICs. The recent demand of serial interconnection technology in the mobile display industry needs delicate impedance control of signal and power traces to prohibit system malfunctioning and to reduce electromagnetic field radiation. Based on the S-parameter and Z-parameter analysis, we analyse the correlation between frequency-domain and time-domain measurements. With multi-port macros, signal integrity can be included in power integrity analysis in time domain.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.213-219
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• 2012

In this paper, we suggested the method of signal integrity for noises and distortion signal generated between high speed information transmission modules by external effects. Suggested method for signal integrity of impedance matching to remove transmission line distortion, We divided the impedance matching between the transmitter and the receiver module with the single line and differential line methods after confirmed the improvement of signal distortions through ADS simulation. the experimental results indicated that it is possible to keep signal integrity without signal distortions by matching the optimal termination impedance which are considering the signal delay of transmission line for using the high-performance modules.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.3-14
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• 2013

In this paper, key design issues and considerations for Signal Integrity(SI) and Power Integrity(PI) of a TSV-based 3D IC are introduced. For the signal integrity and power integrity of a TSV-based 3-D IC channel, analytical modeling and analysis results of a TSV-based 3-D channel and power delivery network (PDN) are presented. In addition, various design techniques and solutions which are to improve the electrical performance of a 3-D IC are investigated.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.63-72
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• 2020

As the design complexity and performances are increased in satellite electronic board, noise related problems are also increased. To minimize the noise issues, various design improvements are performed by power integrity and signal integrity analysis in this research. Static power and dynamic power design are reviewed and improved by DC IR drop and power impedance analysis. Signal integrity design is reviewed and improved by time domain signal wave analysis and PCB(Printed Circuit Board) design modifications. And also power planes resonance modes are checked and mitigation measures are verified by simulation. Finally, it is checked that radiated noise is reduced after design improvements by EMC(Electro Magnetic Compatibility) RE(Radiated Emission) measurement results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.14-19
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• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.35-50
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• 2013

This paper discusses effects of mesh planes on signal integrity in high-speed glass ceramic packages. One of serious signal integrity issues in high-speed glass ceramic packages is high far-end (FE) noise coupling between signal interconnects. Based on signal integrity analysis, a methodology is presented for reducing far-end noise coupling between signal interconnects in high-speed glass ceramic modules. This methodology employing power/ground mesh planes with alternating spacing and a via-connected coplanar-type shield (VCS) structure is suggested to minimize far-end noise coupling between signal lines in high-speed glass ceramic packages. Optimized interconnect structure based on this methodology has demonstrated that the saturated far-end noise coupling of a typical interconnect structure in glass ceramic modules could be reduced significantly by 73.3 %.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.391-394
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• 2008

• ETRI Journal
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• v.41 no.5
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• pp.670-683
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• 2019

In this paper, we analyzed the signal integrity of a system interconnection module for a proposed high-density server. The proposed server integrates several components into a chassis. Therefore, the proposed server can access multiple computing resources. To support the system interconnection, among the highly integrated computing resources, the interconnection module, which is based on Serial RapidIO, has been newly adopted and supports a bandwidth of 800 Gbps while routing 160 differential signal traces. The module was designed for two different stack-up types on a printed circuit board. Each module was designed into 12- (version 1) and 14-layer (version 2) versions with thicknesses of 1.5T and 1.8T, respectively. Version 1 has a structure with two consecutive high-speed signal-layers in the middle of two power planes, whereas Version 2 has a single high-speed signal placed only in the space between two power planes. To analyze the signal integrity of the module, we probed the S-parameters, eye-diagrams, and crosstalk voltages. The results show that the high-speed signal integrity of Version 2 has a better quality than Version 1, even if the signal trace length is increased.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.9-14
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• 2006

Galileo is the European Global Navigation Satellite System, under civilian control, and consists on a constellation of medium Earth orbit satellites and its associated ground infrastructure. Galileo will provide to their users highly accurate global positioning services and their associated integrity information. The elements in charge of the computation of Galileo navigation and integrity information are the OSPF (Orbit Synchronization Processing Facility) and IPF (Integrity Processing Facility), within the Galileo Ground Mission Segment (GMS). Navigation algorithms play a key role in the provision of the Galileo Mission, since they are responsible for computing the essential information the users need to calculate their position: the satellite ephemeris and clock offsets. Such information is generated in the Galileo Ground Mission Segment and broadcast by the satellites within the navigation signal, together with the expected a-priori accuracy (SISA: Signal-In-Space Accuracy), which is the parameter that in fault-free conditions makes the overbounding the predicted ephemeris and clock model errors for the Worst User Location. In parallel, the integrity algorithms of the GMS are responsible of providing a real-time monitoring of the satellite status with timely alarm messages in case of failures. The accuracy of the integrity monitoring system is characterized by the SISMA (Signal In Space Monitoring Accuracy), which is also broadcast to the users through the integrity message.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.20-28
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• 2006

A new TWA(Traveling-wave-based Waveform Approximation)-based signal integrity verification method for practical interconnect layout structures which are composed of non-uniform RLC lines with various discontinuities is presented. Transforming the non-uniform lines into virtual uniform lines, signal integrity of the practical layout structures can be very efficiently estimated by using the TWA-technique. It is shown that the proposed technique can estimate the signal integrity much more efficiently than generic SPICE circuit model with 5% timing error and 10% crosstalk error.