• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.233-236
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• 2000

A portable equipment that measures a current and voltage waveform of power transmission lines is pro-posed. In the equipment, the current and voltage, respectively, are detected by a loop coil and a capacitor clamped around the power lines. The detected data is transmitted by an FM wave to the receiver on the ground station. Since the receiver is isolated from the power lines, we do not require high potential insulators for the measurement of current and voltage. The proposed equipment is therefore, small-sized, light, and low in the cost of production. Experimental results presented here show that the equipment can monitor the current flowing in single wire over a ground plane and the potential of the wire.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1449-1452
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• 2007

배전 케이블 부분방전 측정에서는 외부노이즈, 코로나가 동반되어 검출되고 있다. 특히, 단말부의 부분방전측정에서는 부분방전 현상이 크게 발생하여 측정될 경우 다른 상에서도 유입되어 검출되는데 코로나나 외부의 노이즈가 크게 유입될 경우 진단의 어려움이 있다. 더불어 각 상의 위상을 직접검출이 어려운 송배전 케이블의 단말에서는 유기된 신호의 상을 찾는데도 어려움을 주고 있다. 이러한 문제를 반영하여 현장 측정이 용의하도록 이동형 포터블 진단장치를 개발하였다. 3개의 HFCT 센서를 사용하여 3상을 동시 측정할 수 있도록 하였다. 전원 분압 트리거 회로와 전류 변류 트리거 회로를 사용하여 위상 분석을 병행하였다. 실선로의 배전 케이블 부분방전 진단의 효율적 수행을 위해 개발된 본 장비를 현장 적용하였으며 내장된 PRPD 분석법이 가능하였으며 S/W 노이즈 게이팅을 적용하여 다른상에서 유기되는 신호를 제거하여 진단결과의 신뢰성을 높일 수 있었다.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• Journal of Communications and Networks
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• v.14 no.2
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• pp.179-187
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• 2012

Power saving is one of the most important features that extends the lifetime of portable devices in mobile wireless networks. The IEEE 802.16e mobile broadband wireless access system adopts a power saving mechanism with a binary truncated exponent algorithm for determining sleep intervals. When using this standard power saving scheme, there is often a delay before data packets are received at the mobile subscriber station (MSS). In order to extend the lifetime of a MSS, the battery energy must be used efficiently. This paper presents a dynamically alternating sleep interval scheduling algorithm as a solution to deal with the power consumption problem. We take into account different traffic classes and schedule a proper sequence of power saving classes. The window size of the sleep interval is calculated dynamically according to the packet arrival rate. We make a tradeoff between the power consumption and packet delay. The method achieves the goal of efficiently reducing the listening window size, which leads to increased power saving. The performance of our proposed scheme is compared to that of the standard power saving scheme. Simulation results demonstrate the superior performance of our power saving scheme and its ability to strike the appropriate performance balance between power saving and packet delay for a MSS in an IEEE 802.16e mobile broadband wireless access system.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.11
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• pp.503-507
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• 2005

Both ratio error and phase angle error in voltage transformer(VT) depend on values of VT burden used. Thus, precise measurement of burden is very important for the evaluation of VT. A method of evaluation for VT burden has been developed by employing the portable decade resistor, with AC-DC resistance difference less than 10-3. The burden value(value and power factor) can be obtained by conductance and susceptance, obtained by measuring the change of ratio error and phase angle error caused by the resistance change of decade resistor. The burden value and power factor obtained by the method are consistent with those obtained using power analyzer within corresponding uncertainties.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.31-34
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• 2004

In wireless communication systems, low-power metrics is becoming a burdensome problem in the portable terminal design, because of portability constraints. This paper presents design architecture of a low-power partial correlation Digital Matched Filter for the IMT-2000 communication systems. The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. The proposed architecture was verified by using Xilinx FPGA.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.2
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• pp.231-234
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• 2009

Recently, to the development of a highly information-oriented society to a large increase in dependence on power, Accordingly, it is need that active development and spread of preservation technology on accident prevention in operation electrical equipment. However, to lack of the use on maintenance technology of power equipment and to increase of power usage is growing deterioration of power equipment, this is a cause on casualties, property damage and the occurrence of disasters is a growing. GIS equipments which are operated from domestic except the equipment which manages from the big business are depend on a most visual inspection, and do inspection method or measuring instrument etc. a condition which is not supplied widely. Currently, many to measure instrument used in domestic is very expensive or foreign, it will be able to substitute this, the development necessity of the diagnosis technique and the measuring instrument is demanded.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3058-3060
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• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.138.6-138
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• 2001

In recent years, as the battery-powered portable systems such as cellular phone, personal digital assistant (PDA) are widely used, power consumption comes to be a top-priority design concerns. Because those embedded systems become more and more complex than ever and they are operated under severe power and energy constrains, long battery lifetime with a limited energy is very critical. Even though there are various levels of energy optimization techniques, system level techniques are mainly focused on, for their stronger impact on power consumption of the overall system than traditional techniques : circuit level, switch level, architecture level, etc. In this technique, operating system (OS) plays the most important role in the system because it controls ...