• Journal of Power Electronics
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• 제8권3호
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• pp.201-209
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• 2008

This paper presents the modeling and design of a digital controller for a phase-shifted full-bridge converter (PSFBC) in a discrete-time domain. The discretized PSFBC model is first derived and then analyzed considering the sampling effect and the system parameters. Based on this model, the digital controller is directly designed in a discrete-time domain. The simulation and experimental results are provided to show the validity of the proposed modeling and controller design.

• 전력전자학회논문지
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• 제18권5호
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• pp.501-506
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• 2013

A hold-up time compensation circuit is proposed to get high efficiency of the front-end phase-shifted full bridge DC/DC converter. The proposed circuit can make the phase-shifted full bridge front-end DC/DC converter built with 0.5 duty ratio so that the conduction loss of the primary side and voltage stress across rectifier in the secondary side are reduced and the higher efficiency can be obtained. Furthermore, the requirement of an output filter significantly can diminish due to the perfect filtered waveform. A 12V/100A prototype has been made and experimental results are given to verify the theoretic analysis and detailed features.

• 전력전자학회논문지
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• 제26권5호
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• pp.372-375
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• 2021

A three-leg inverter-type isolated DC-DC Converter that can use 220 and 440 V grid input voltages is introduced. The secondary circuit structure of the proposed topology is center-tap, which is the same as the conventional phase-shifted full-bridge converter. However, the primary circuit structure is composed of a three-leg inverter structure and a transformer, in which two primary windings are connected in series. The proposed circuit structure has a wider input voltage range than the conventional phase-shifted full-bridge converter, and the circulating-current on the primary-side is reduced. In addition, the voltage stress at the secondary rectifier is greatly improved, and high efficiency can be achieved at a high input voltage by removing the snubber circuit added to the conventional converter. Prototype converters with input DC of 311 V, output of 622 V, and 50 V and 6 kW class specifications were designed and manufactured to verify the validity of the proposed topology; the experimental results are presented.

• Journal of Power Electronics
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• 제17권1호
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• pp.31-40
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• 2017

A novel voltage-fed single-stage power factor correction (PFC) full-bridge converter based on asymmetric phase-shifted control for battery chargers is proposed in this paper. The attractive feature of the proposed converter is that it can operate in a wide output voltage range without an output low-frequency ripple, which is indispensable in battery charger applications. Meanwhile, the converter can maintain a high power factor and a controllable dc bus voltage over a wide output voltage range. In this paper, the realization of PFC and the operation principle of asymmetric phase-shifted control are given. A small-signal analysis of the proposed single-stage power factor correction (PFC) full-bridge converter is performed. Experimental results obtained from a 1kW experimental prototype are given to validate the feasibility of the proposed converter. The PF is higher than 0.97 over the entire output voltage range with the proposed control strategy.

• 전력전자학회논문지
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• 제20권6호
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• 전력전자학회논문지
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• 제26권3호
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• pp.237-240
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• 2021

This research proposes a new rectifier circuit to reduce the circulating current of a phase-shifted full bridge converter. The proposed circuit is a structure in which the output inductor of the secondary rectifier circuit is changed to a coupled inductor in the phase-shifted full bridge with the existing center-tapped rectifier. The parts are rearranged after adding a diode. After applying the proposed circuit, the circulating current to the primary current of the transformer and the voltage stress of the rectifier diode on the secondary side of the transformer are reduced. Accordingly, the snubber loss of the rectifier is improved. By reducing the circulating current and snubber loss, the circuit achieves higher efficiency than conventional circuits. In this research, we present the structure of the proposed circuit, its strengths, and the analysis results from experiments. Furthermore, its effectiveness is verified through the experimental results of a prototype converter with an input of 300-400 V and an output of 50 V/1 kW.

• Journal of Power Electronics
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• 제15권3호
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• pp.634-643
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• 2015

This paper presents a high frequency design approach for improving efficiency over a wide load range in the self-driven phase-shifted full-bridge converters for server power systems. In the proposed approach, a detailed ZVS analysis of the lagging leg switches in both the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) is presented. The optimum dead time and the determination of the appropriate operation mode are given for high efficiency according to the load conditions. Finally, the optimum operation conditions are defined to achieve a high-efficiency. A laboratory prototype operating at 80 kHz, rated 1 kW (12 V-83.3 A), is built to verify proposed theoretical analysis and evaluations. The experimental results show that the maximum efficiency is achieved as 95% and 83.5% at full load and 5% load conditions, respectively.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.22-24
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• 2006

Of all the proposed resonant techniques, the well-known phase-shifted full bridge converter remains one of the most attractive because it offers an easy way of achieving ZVS with a minimum of extra components added, which is essential for the high power applications. This paper describes the design of a digital controller for a Phase Shifted Full-bridge PWM Converter. The small-signal model is derived incorporating the effects of phase-shift control and the utilization of the transformer leakage inductance and power FET junction capacitances to achieve the zero-voltage resonant switching. Based on the derived small-signal model, the digital controller is designed in the discrete domain. The performance of designed controller is verified through the simulation.

• 전력전자학회논문지
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• 제6권3호
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• pp.265-272
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• 2001

기존의 전자레인지의 마그네트론 구동용 전원장치는 성층 철심을 사용한 60[Hz]고압 변압기, 큰 용량의 콘덴서와 싸이리스터를 이용한 위상제어 회로를 사용하기 때문에 부피가 크고 무거우며, 저효율의 단점을 가지고 있다. 본 논문은 출력 600[W]마그네트론을 장착한 전자레인지의 전원장치로 최대출력1[kW], 스위칭 주파수20[kHz]의 Phase-shifted Full-Bridge(FB)Zero-Voltage-Switched(ZVS) PWM 컨버터의 사용을 제안하고, 이를 개발.적용하여 전체 시스템의 경량화 및 고전력밀도의 목적을 달성하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.346-347
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• 2019

본 논문에서는 3.3 [kW] on-board charger (OBC) 용 phasw-shifted full-bridge (PSFB) 컨버터의 고효율 및 고전력 밀도 달성을 위한 스위칭 주파수 설계 방안을 제안한다. 스위칭 주파수에 따라 달라지는 손실 양상 및 전력 밀도에 대해 분석하기 위해 각 스위칭 주파수 별 반도체 소자 손실과 수동 소자 손실을 계산하고, 수동 소자의 부피 변화에 따른 전력밀도 변화를 분석한다. 분석 결과를 바탕으로 고효율 및 고전력밀도 달성을 위한 시스템 설계 포인트를 선정하고 시뮬레이션을 통하여 설계 결과를 검증한다.