• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.43-51
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• 2020

In this paper, the design of 64 array antennas applied to RWP (Radar Wind Profiler) was described. The design point of the antenna is to ensure isolation between each element and to match the vertical / horizontal radiation pattern. To this end, a single element of the array antenna was proposed as a Bend dipole type, and through simulation, When sequentially sending 5 beams including vertical, the east/west/south/north direction was ±20°, and it was confirmed that no Grating Lobe occurred when steering the beam. The 64 array antenna proposed in this paper was designed with performance equal to or higher than that of overseas products, and was confirmed to be applicable to RWP.

• Korean Journal of Food Science and Technology
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• v.31 no.5
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• pp.1386-1391
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• 1999

The methanol extract of Gardenia jasminoides Ellis showed antimicrobial activity against bacteria and yeasts. The extract was successively purified with solvent fractionation, silica gel adsorption column chromatography, Sephadex LH-20 column chromatography, octadecylsilane column chromatography. The purified active substance was isolated by high performance liquid chromatography. The isolated compound was 3,4-dihydroxybenzoic acid which was determined by mass spectrometer, gas chromatograph-mass spectrometer, $^{1}H-nuclear$ magnetic resonance, $^{13}C-nuclear$ magnetic resonance and two-dimensional nuclear magnetic resonance. The content of 3,4-dihydroxybenzoic acid was $32.7\;{\mu}g/g$ in dried fruits of Gardenia jasminoides Ellis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.117-118
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• 2008

High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.149-157
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• 2017

In this paper, we propose BCMR (Block Classification with Monitor and Restriction) to ensure the isolation and to reduce the interference of blocks between a garbage collection and a wear leveling. The proposed BCMR monitors an endurance variation of blocks during the garbage collection and detects hot blocks by making a restriction condition based on this information. The proposal induces a block classification by its update frequency for the garbage collection and the wear leveling, so we will get a prolonged lifetime of NAND flash memory systems. In a performance evaluation, BCMR prolonged the lifetime of NAND flash memory systems by 3.95%, on average and reduced a standard deviation per block by 7.4%, on average.

• Journal of electromagnetic engineering and science
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• v.9 no.2
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.7
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• pp.806-813
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• 2016

To alleviate the vibration problem or to satisfy the required criteria for manifesting the guaranteed performance of precise equipment, various vibration isolation materials or apparatus, such as viscoelastic material, air and coil spring, have been developed and applied. Among them, a wire mesh material is regarded as one of the good candidate for reducing the vibration in terms of moderate material price, easy shape machining and long life cycle without the property deterioration induced by the aging or environmental effects. In this paper, prior to wire mesh isolator design, the static and dynamic elastic modulus of wire mesh materials are extracted from the experiment by the simple shaped cylindrical specimens and their characteristics for applying to vibration isolator design are examined. The simple shaped specimens were made as considering the design parameters of a wire mesh mount; i.e. the density, wire diameter and wire mesh slope, and the sensitivity analysis were also performed from a view point of the extracted elastic modulus.

• Architectural research
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• v.14 no.3
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• pp.99-108
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• 2012

An innovative multi-story Semi-Active Tuned Mass Damper (SATMD) building system is proposed to control seismic response of existing structures. The application of adding new stories as large tuned mass and semi-active (SA) resettable actuators as central features of the control scheme is derived. For the effective control of the structures, the optimal tuning parameters are considered for the large mass ratio, for which a previously proposed equation is used and the practical optimal stiffness is allocated to the actuator stiffness and rubber bearing stiffness. A two-degree-of freedom (2-DOF) model is adopted to verify the principal efficiency of the suggested structural control concept. The simulations for this study utilizes the three ground motions, from SAC project, having probability of exceedance of 50% in 50 years, 10% in 50 years, and 2% in 50 years for the Los Angeles region. 12-story moment resisting frames, which are modified as '12+2' and '12+4' story structures, are investigated to assess the viability and effectiveness of the system that aims to reduce the response of the buildings to earthquakes. The control ability of the SATMD scheme is compared to that of an uncontrolled and an ideal Passive Tuned Mass Damper (PTMD) building system. From the performance results of suggested '12+2' and '12+4' story retrofitting case studies, SATMD systems shows significant promise for application of structural control where extra stories might be added.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.12
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• pp.1042-1047
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• 2003

The goal of this research is to implement a PC-based remote control system of ion implanter using Visual Basic programming. Presently, skilled process engineers are required to regularly setup and adjust implanter parameters. Any reduction in the number of production hours devoted to ion beam implanter setup or recalibration after a species change would represent substantial improvements in both manpower and equipment utilization. An optical communication system for the remote control and telemetry in the operation of the 50kev potential was designed and constructed. This system enables continuous and safe operation of the ion implanter and can be the basis for the automation. The isolation characteristics of optical fiber were 10kV/cm, and performance tests of the system under the intense noise environment during the implanter operations showed satisfactory results. This system is designed to completely replace the existing human-machine interface with many new functions. This paper describes the important components of the system including system architecture and software development. It is expected that this system can be used for the communication and control purpose in the high noise environments such as the operation of the MeV energy implanter or other high power, high noise systems.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.