• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.31 no.3
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• pp.264-271
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• 1995

This paper presents the data parallel processing method between a PC and a micro-controller. To implement the method a dual port RAM for a real time data processing is used. In general an A/D & D/AC card is used to send or receive the data into or from the external plant and the PC does only the computation of the A/D and the D/A data because the A/D & D/AC card does not have the ability of computation. In this study, a data parallel processing method in which the PC and micro-controller own a common dual port RAM, is introduced, so that the PC can compute the A/D and D/A data and control the plant simultaneously. The PC system with a micro-controller and the common dual port RAM is designed and its effectiveness is investigated experimentally considering the performance of both the computation of data and the controlling and monitoring the external plant.

• Computational Structural Engineering
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• v.5 no.3
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• pp.52-55
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• 1992

이 글에서는 Mathematica의 고유한 특징과 많은 기능 중의 일부분만을 예를 들어 설명을 하였다. 그러나 Mathematica의 피할 수 없는 단점은 많은 수학적 기능이 포함되어 있기 때문에 처리속도가 늦다는 점이다. 예를 들면 많은 량의 반복작업이나 차수가 큰 매트릭스의 연산작업은 다소 속도가 늦어 PC기종에서는 곤란을 겪을 때가 많다. 따라서 PC대신 workstation 같은 상위기종의 컴퓨터를 이용한다면 처리속도가 빨라져 진행에 문제점이 없다. 한 예로 workstation에서는 차수가 30개인 고유치 해석도 내장함수인 명령어만으로 단지 몇초만에 할 수 있는 데 비하여 PC에서는 기종에 따라 몇배, 몇백배의 시간이 요구되는 것이다. 그리고 또 하나의 단점으로는 방대한 프로그램을 운용하기 위한 비용(ram)이 많이 든다는 점이다. 한 예로 PC에서는 기본적으로 Mathematica를 작동하기 위해 최소한 4 mega ram이 필요하며 여러 수학적 기능을 충분히 이용하기 위해 많은 량의 ram이 필요하다는 점이다. 그러나 위의 단점은 Mathematica가 지니고 있는 고유한 장점을 생각한다면 매우 미미한 것이라 여겨진다. 수학의 대부분의 기능을 포함하고 있으며 기호처리가 가능하고 프로그래밍 기법이 다양하기 때문에 수학을 이용하여 연구를 하는 사람에게는 훌륭한 도구가 생긴 것이라 할 수 있다.

• Digital Contents
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• no.9 s.124
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• pp.178-187
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• 2003

삼성전자가 본격적인 디지털 녹화 시대 개막을 알리는 램(RAM)방식의 DVD레코더(모델명:DVD-R5000)를 국내에 출시한다. 삼성전자가 이번에 출시하는 램(RAM)방식의 레코더는 PC를 기반으로 하고 있기 때문에 녹화와 재생 등이 타 방식보다 빠르다는 것이 가장 큰 특징이다. 즉 디스크에 기록된 영상과 음성등을 가장 빨리 찾고, 재생할 수 있다는 점이다.

• Journal of the Korean Magnetics Society
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• v.22 no.5
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• pp.162-166
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• 2012

V-I characteristics of Fe(100)/MgO(100)/Cu-phthalocyanine (CuPc)/Co hybrid magnetic tunnel junctions were investigated at different temperatures. Fe(100) and Co ferromagnetic layers were separated by an organic-inorganic hybrid barrier consisting of different thickness of CuPc thin film grown on a 2 nm thick epitaxial MgO(100) layer. As the CuPc thickness increases from 0 to 10 nm, a bistable switching behavior due to strong charging effects was observed, while a very large magenetoresistance was shown at 77 K for the junctions without the CuPc barrier. This switching behavior decreases with the increase in temperature, and finally disappears beyond 240 K. In this work, high-potential future applications of the MgO(100)/CuPc bilayer were discussed for hybrid spintronic devices as well as polymer random access memories (PoRAMs).

• Journal of IKEEE
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• v.28 no.3
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• pp.365-368
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• 2024

This paper proposes a scheme for NAND flash memories equipped with on-chip microcontrollers and instruction ROM, that enables patching of erroneous cell array operation instructions after manufacturing. The scheme incorporates a small patch instruction RAM, where the patching instructions are fetched using a configurable Program Counter (PC) substitution mechanism. Both the patching instructions and PC substitution data are stored in a designated NAND cell area and loaded at power-up along with the electrical fuse data. As the scheme is designed to handle only a small number instruction patches, the area overhead remains minimal.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.35-40
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• 2010

NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.

• Journal of The Korean Association of Information Education
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• v.22 no.5
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• pp.605-611
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• 2018

On-Line Lectures are becoming more common due to the MOOK service and the expansion of national policy in Korea. Especially, It is being changed to new remote mixed style from traditional lecture in universities. We propose and implement a remote contents making tool with audio synchronization function based on more with less resources. To implement our proposed algorithm, we design an interactive interface to assign multiple cutting intervals and convert an input video to print a new result. In experimental, we can confirm our algorithm works properly with average performance value 9.3% cpu share ratio and 87mega byte ram usage(CPU 2.60GHz, 820*600 Area).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.10
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• pp.857-867
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• 1990

Sine CAM structure is regular structure as that of RAM of PLA, CAM generator program is easy to implement. This program outputs CAM layout in the form of CIF(Caltech Intermediate Format) and graphic display program is debugging or displaying CAM generator output, which are implemented on PC/AT with MS C(5.0) graphic library and C language. CIF parser is programmed with YACC(Yet Another Compiler Compiler) and LEX (Lexical Analyzer) in order to flat the CIF data. For the purposed of plotting the layout output using ROLAND XY plotter is developed. By combining these program described above, from CIF generation to layout plotting can be executed on pull-down menu according to user's option.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.6 no.4
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• pp.20-27
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• 1995

A numerical simulation is carried out on the directivity synthesis of ultrasonic transducers by point source array. Gauss elimination method is practiced by means of a directive method to realize the desired directivity. Desired directivity is chosen to be that of a directivity of line source, a beam width and a direction arbitrary specified. On the numerical result, Gauss elimination method is showed high speed ca- lculative simulation and stability of system more than iterative method(LMS, DFP). Numerical simulations are carried out by PC(CPU:80486 DX2, RAM 16Mbyte).

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.