• Proceedings of the KSMRM Conference
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• 2002.11a
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• pp.76-76
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• 2002

Purpose： The purpose of this study is to optimize the configuration of body RF coil composed of 4 planar subcoils for low field open MRI. Method： Our low field RE coil is composed of 4 subcoils assumed to be located at both the bottom and top sides of permanent magnet. Each subcoils has 3 main strips. The coil system has mirror inversion symmetry. First, the currents on the strips are obtained by inductance calculation and circuit analysis, Second, all the strips are divided into line strip elements across the strips, the self Inductances of line strip elements and the mutual inductances among the line strip elements are calculated, and current distributions of strip are obtained by circuit analysis, where each strip is considered as parallel combination of line strip elements. Finally all the line strip elements are segmented, magnetic field has been calculated by pseudo electric dipole radiation method, where the current elements are regarded as pseudo electric dipole radiation sources. We have performed above procedures for various configurations of RE coil. The field homogeneity is calculated in the 25 cm DSV.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.11
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• pp.768-775
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• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Journal of Information Display
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• v.2 no.2
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• pp.1-6
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• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• Proceedings of the KIEE Conference
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• 1998.07e
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• pp.1647-1649
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• 1998

This paper describes the power frequency voltage and its countermeasure when a 765 kV transmission line is directly connected to a 345 kV line and operated at 345 kV voltage. The summary of this result is as follows : The western route of 765 kV transmission line doesn't need any countermeasure to reduce the power frequency voltage at the receiving end. The eastern route of 765 kV transmission needs 100 Mvar(3 phase) capacity of shunt reactor at the receiving end to reduce the power frequency voltage. The use of shunt reactors in the 765 kV transmission lines has unexpected problems, one of which is induction of high voltages on a de-energized circuit of two parallel lines. This paper examined the problem of resonance on two parallel transmission circuits in one routes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.318-324
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• 1997

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, a linear resistor, and a nonlinear resistor. In this papre we analyze a circuit obtained by replacing the parallel LC resonator in the Chua's circuit by lossless transmission line. By using the method of characteristics of this circuit we show that various periodic motions and chaotic motions can the attained according to parameter variations. From Chua's circuit with a lossless transmission line a variely of chaotic attractors which are similar to those of the normal Chua's circuit are observed.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.921-926
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• 2015

For the over-heat protection purpose in power strip devices, over-current detection/protection circuits, such as bimetal, switching circuit, and microprocessor-based relay circuit, have been widely setup in high-end products. Most of these circuits are connected to the power line in parallel and, thus, they are sensitive to the line voltage and current distortion. Moreover, these protection circuits are often costly and, therefore, it is hard to meet the commercial requirements. A low-cost over-current detection circuit with the contactless current transducer is designed and tested in this paper. The detection circuit is galvanically isolated from the power line and, thus, less sensitive to the line voltage distortion. The experimental results show that the proposed circuit accurately operates despite of its simple structure and low-cost electronic parts.

• Proceedings of the KIEE Conference
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• 1999.11b
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• pp.255-257
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• 1999

Fault location algorithms based on the current distribution factors under the one-phase to earth fault condition of a double-circuit line are presented. The derivation method for current distribution factors is showed, to calculate fault current, fault resistance and the zero sequence current of other parallel circuit which are unknown. As the proposed algorithms 1,2,3 embodies an accurate location by the voltage and the current of the relaying point.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.50 no.3
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• pp.146-152
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• 2001

This paper describes an accurate fault location algorithm based on sequence current distribution factors for a double-circuit transmission system. The proposed method uses the voltage and current collected at only the local end of a single-circuit. This method is virtually independent of the fault resistance and the mutual coupling effect caused by the zero-sequence current of the adjacent parallel circuit and insensitive to the variation of source impedance. The fault distance is determined by solving the forth-order KVL(Kirchhoff's Voltage Law) based distance equation. The zero-sequence current of adjacent circuit is estimated by using a zero-sequence current distribution factor and the zero-sequence current of the self-circuit. Thousands of fault simulation by EMTP have proved the accuracy and effectiveness of the proposed algorithm.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.317-319
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• 2006

This paper proposes a fault location algorithm for two-parallel transmission line in the case of single line-to-ground fault Proposed algorithm is using voltage and current measured in the sending-end. The fault distance is simply determined by solving a second order polynomial equation due to the direct circuit analysis. The simulations by PSCAD/EMTDC have demonstrated the accuracy and effectiveness of the proposed algorithm.

• Journal of electromagnetic engineering and science
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• v.6 no.3
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• pp.171-175
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• 2006

In this paper, a new semi-lumped low-pass filter with three finite attenuation poles at stopband is presented. The new structure is composed of a pair of symmetrical parallel coupled-line and a shunted capacitor. With this configuration, three finite attenuation poles can be available for 2nd, 3rd, and 4th harmonics suppression. The research method is based on transmission-line model for tuning the attenuation poles. In order to examine the feasibility of the proposed structure, a low-pass filter based on microstrip structure with harmonics suppression is designed, fabricated, and measured. The experimental results of the fabricated circuit agree well with the simulation and analytical ones.