• International Journal of Precision Engineering and Manufacturing
• /
• v.6 no.3
• /
• pp.24-28
• /
• 2005

Stress state of chip formation zone is one of the main problems in metal cutting mechanics. In two-dimensional case this process is usually considered as consistent shears of work material along one of several shear surfaces, separating chip from workpiece. These shear planes are assumed to be trajectories of maximum shear stress forming corresponding slip-line field. This paper suggests a new approach to the constriction of slip-line field, which implies uniform compression in chip formation zone. Based on the given model it has been found that imaginary shear line in orthogonal cutting is close to the trajectory of maximum normal stress and the problem about its determination has been considered as well. It has been shown that there is a second central slip-line field inside chip, which corresponds well to experimental data about stress distribution on tool rake face and tool-chip contact length. The suggested model would be useful in understanding mechanistic problems in machining.

• ETRI Journal
• /
• v.19 no.3
• /
• pp.228-241
• /
• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.8
• /
• pp.1564-1573
• /
• 2007

Bulk of toner residual quantity detection return trip conglutinated in toner of using printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. Return trip this development miniaturizes such as this by doing one chip competitive product develop chip has to be conglutinated compulsorily in toner used to printer announced since 2005 years. Therefore, demand of chip to be used in forward revival market may be thriving. Production of revival toner is impossible by chip conglutinated to printer to meaning that manage information of toner cut ridge that universal laser printer makers are used in printer and do customer service. In this paper, we develops chip conglutinated compulsorily to produce revival toner.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.9
• /
• pp.259-269
• /
• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.12
• /
• pp.1148-1157
• /
• 2013

In a passive UHF RFID system, the impedance matching between tag antenna and chip as well as the protocol parameter settings in a reader plays important role in determination of the maximum read-range. Almost no paper, however, has dealt with the above issues in relation with the maximum read range. In this paper, two known methods (of using the value from data sheets and proprietary RFID tester) and our proposing method in chip impedance evaluation are compared in terms of maximum read range. The read range of tags whose antenna impedance is conjugate matched with the chip impedance obtained from the proposed method is improved maximum 73 % more than that of tags from the other methods.

• Journal of the Korean Society for Precision Engineering
• /
• v.23 no.5 s.182
• /
• pp.155-161
• /
• 2006

This paper introduces a new type of mechanical tape feeder for chip mounter. The mechanical feeder is composed of a pneumatic linear actuator and a linear feeding module with the application of a cam-slider. As semiconductor chips are getting smaller, PCB assembly makers require the feeder to position the chip with high accuracy. The linear feeding system improves the positioning accuracy of the chip by getting rid of the index error, which brings into existence on the sprocket rotating feeder. It also can make greatly reduce the dumping rate. The dumping error is caused by the impact occurred as the pawl to interrupt ratchet wheel rotation. The paper discusses its mechanism and mechanical performance. The positioning accuracy and the dynamic characteristic were measured for long time operation and analyzed. As a result, the feeder showed very good performance. However, the feeding system was dynamically unstable due to the cover film eliminator that is required to be modified

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.2
• /
• pp.149-158
• /
• 1996

In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

• ETRI Journal
• /
• v.22 no.1
• /
• pp.20-29
• /
• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.1
• /
• pp.64-69
• /
• 2005

In this paper, we analyzed the nonlinear performance on the DS/CDMA Communication System. At the $BER=10^{-4}$, uniform chip waveforms have similar performance in the linear channel. However, non-uniform chip waveforms have about more 0.5[dB] power gain than the conventional raised-cosine chip waveforms. In the nonlinear HPA, non-uniform chip waveforms have worse BER performance than the uniform chip waveforms because of the high PAPR. In other words, non-uniform chip waveforms show similar performance as uniform chip waveforms if IBO (input back on) of 15[dB] is given.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.8 no.3
• /
• pp.437-443
• /
• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.