• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.3
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• pp.217-223
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• 2013

A digital retrodirective antenna system is easy to modify and upgrade because it can control the phase information of the output signal toward opposite direction to input signal without a priori knowledge of the arrival direction. Due to this advantage, it is possible to perform fast beam tracking. In this paper, a design digital retrosirective array antenna system according to the number of antenna array by using only one digital PLL which finds angle of delayed phase and we test BER performance of this system. When we transmit data at actual communication system, the data modulated onto carrier frequency in order to shift spectrum from base band to another band. So we simulate system considering carrier frequency according to the number of antenna array. As a result, carrier frequency has no impact on the performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.2
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• pp.209-216
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• 2013

In this paper, we design and analyze digital retrodirective array antenna (RDA) system in 60GHz wireless communication for low power consumption and high quality. Digital RDA can automatically make beam toward source without information about the direction of incoming signal, this system is able to do low power communication thanks to increased signal to interference noise ratio (SINR) because making the beam toward source can reduce interference signals. The frequency offset seriously arises when millimetric wave band like 60GHz is used to communicate for high-speed transmission. The proposed system is robustly designed to frequency offset through designing digital phase lock loop in order to solve the problem of frequency offset. In this paper, we analyze the performance of the proposed system according to the number of array antenna and frequency offset. striking space.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.502-511
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• 2012

As the importance of GNSS system increases, the necessity of independent system is increased also. When the independent GNSS system is required, GNSS signal design is necessary with requirement definition. This paper suggests the design method of GNSS signal using the analysis result of receiver performance. First, the candidates are defined based on the design elements. Then the receiver performance of the candidates is analyzed based on the performance evaluation parameters. The weights of performance evaluation parameter are defined in order to consider the receiver performance in a various aspects. Finally, the calculation of normalized performance evaluation parameters and weights are derived to obtain the compared value for signal selection. Spreading code, modulation method and carrier frequency are considered as design parameters. Also, correlation width, DLL PLL thermal noise jitter, frequency bandwidth and side lobe peak ratio are considered as performance evaluation parameters. And positioning performance, robustness to noise, bandwidth efficiency are considered as the performance aspects. This paper analyzes the performance of each candidate using software based simulator and suggest the method to compare objectively the performance of each candidates.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.107-110
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• 2005

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1120-1135
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• 2005

In this paper, We have design and implement the network synchronization module for NG-SDH system having 120 Gbps capacity. and also evaluate the performance of it. We also propose analyzing algorithm clock characterisrics on NG-SDH node clock based on the evaluation results.