• Title/Summary/Keyword: PLL Frequency Synthesizer

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Improvement of Phase Noise in Frequency Synthesizer with Dual PLL (이중 PLL 구조 주파수 합성기의 위상 잡음 개선)

  • Kim, Jung-Hoon;Park, Beom-Jun;Kim, Jee-Heung;Lee, Kyu-Song
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.9
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    • pp.903-911
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    • 2014
  • This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

Analysis of the effect of Digital frequency synthesizer in FSK-Frequency-hopped data communications (FSK-주파수 도약 데이터 통신시스템에서의 디지털 주파수 합성기의 영향분석)

  • 송인근
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.879-886
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    • 2003
  • Agile frequency synthesizers are the common device used for commandable, wide-band frequency hopping in frequency-hopped (FH) communications. In this paper, synthesizer phase transient effect and its compensation methods in an FH/FSK(Frequency Hopped Frequency Shift Keying) system are studied. Models for these analysis are developed and resulting performance degradations are computed. The basic PLL is difficult to implement for fast frequency hopping in narrowband radio communication systems. To solve this problem, digital frequency synthesizer/CPM (Continuous Phase Modulation)modulator is proposed. And it's performance is analyzed theoretically. The analysis show that fast frequency hopping is possible in frequency hopping system that use digital frequency synthesizer/CPM modulator.

Design of PLL Frequency Synthrsizer for Data Link Communication (데이터링크 통신을 위한 PLL 주파수합성기 설계)

  • Kwon, Sang-Chul;Kang, Kyung-Sik
    • Journal of the Korea Safety Management & Science
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    • v.17 no.3
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    • pp.377-381
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    • 2015
  • For the first time, PLL frequency synthesizer using DDS was adapted for the data link communication system which should fast transmit and receive each other with the correct information and fast Hopping System. It is inevitable to lost the synchronization by slow lock time about PLL and no cut off the noise. This paper propose the design of PLL frequency synthesizer which can make 800MHz frequency range. The PLL frequency synthesizer has three high qualities those are frequency accuracy, fast lock time and outstanding phase noise.

Design of a PLL Frequency Synthesizer for RSSI Applications Using Phase Noise Analysis (위상잡음 해석을 이용한 RSSI용 PLL 주파수합성기 설계)

  • Kim, Nam-Tae;Jeong, Jae-Han;Song, Han-Jung
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.48 no.12
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    • pp.28-34
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    • 2011
  • In this paper, a PLL frequency synthesizer for RSSI applications is designed by phase noise analysis. Required synthesizer performance is achieved by optimizing the noise performance of PLL components and a loop transfer function, since its phase noise, lock time, and spur suppression capability are determined by the performance of loop components and loop filter characteristics. As an application example, a PLL frequency synthesizer for RSSI applications, which operates at the frequency of 2.288GHz, is designed using the phase noise analysis. The validity of the design technique is proved by experiments.

Applications of Triple Controlled Type DDFS-driven PLL Frequency Synthesizer to Broadband Wireless Systems (3중조절 DDFS 구동 PLL 주파수 합성기의 광대역 무선 통신시스템에 응용)

  • Heung-Gyoon Ryu;Byeong-Rok An
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.13 no.6
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    • pp.546-551
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    • 2002
  • In this paper, a triple controlled type DDFS-driven PLL frequency synthesizer with reduced complexity is used to show its applications for broadband wireless communication systems by frequency synthesis control. Since the proposed DDFS-driven PLL synthesizer is very simplified to use only phase accumulator in DDFS, it improves the switching speed and power consumption than the conventional DDFS-driven PLL frequency synthesizer. It is appropriate for applications with requirements of broadband, low-power consumption and high switching speed, since the proposed synthesizer can cover a wide range of frequency bands by the triple frequency control parameters. Method and results of frequency control parameters assignment are shown for the several frequency bands applications such as GSM, IMT-2000, Bluetooth and PCS system.

A 166MHz Phase-locked Loop-based Frequency Synthesizer (166MHz 위상 고정 루프 기반 주파수 합성기)

  • Minjun, Cho;Changmin, Song;Young-Chan, Jang
    • Journal of IKEEE
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    • v.26 no.4
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    • pp.714-721
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    • 2022
  • A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

Design and Implementation of a Novel Frequency Modulation Circuit using Phase Locked Synthesizer (PLL Synthesizer를 이용한 새로운 FM 회로 설계 및 제작)

  • Yang, Seong-Sik;Lee, Jong-Hwan;Yeom, Kyung-Whan
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.224-228
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    • 2003
  • In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

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A Study on the Design and Implementation of Ku-Band Frequency Synthesizer by using PLL (PLL을 이용한 Ku-Band 주파수 합성기 설계 및 제작에 관한 연구)

  • 이일규;민경일;안동식;오승협
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.10
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    • pp.1872-1879
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    • 1994
  • The design and implementation of Ku-Band frequency synthesizer was accomplished by the use of PLL and frquency multiple method. Design procedure and operation characteristics of PLL circuit were analyzed on the basis of control theory to synthesize about 1 GHz frequency which should be stable. By connecting frequency doubler and frequency eighth multiplier to the designed PLL circuit in series, Ku-Band frequency was synthesized. The validity of design method of Ku-Band frequency synthesizer was verified through experimental results.

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Design and Fabrication of a Offset-PLL with DAC (DAC를 이용한 Offset-PLL 설계 및 제작)

  • Lim, Ju-Hyun;Song, Sung-Chan
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.2
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    • pp.258-264
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    • 2011
  • In this paper, we designed a frequency synthesizer with a low phase noise and fast lock time and excellent spurious characteristics using the offset-PLL(Phase Locked Loop) that is used in GSM(Global System for Mobile communications). The proposed frequency synthesizer has low phase noise using three times down conversion and third offset frequency of this synthesizer is created by DDS(Direct Digital Synthesizer) to have high frequency resolution. Also, this synthesizer has fast switching speed using DAC(Digital to Analog Converter). but phase noise degraded due to DAC. we improved performance using the DAC noise filter.

Communication Performance Analysis and Characteristics of Frequency Synthesizer in the OFDM/FH Communication System (OFDM/FH 통신시스템에 사용되는 주파수 합성기의 특성과 통신 성능 분석)

  • 이영선;유흥균
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.8
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    • pp.809-815
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    • 2003
  • It is very important to get very high switching speed as well as low phase noise of frequency synthesizer in the OFDM/FH communication system. In this paper we compare the phase noises and switching speeds of the conventional PLL and digital hybrid PLL(DH-PLL) frequency synthesizer, also, we investigate the effect of phase noise on the performance of OFDM/FH communication system. DH-PLL has high switching speed property at the cost of circuit complexity and more power consumption. Unlike the conventional PLL in which the phase noise and switching speed have the trade off relationship in respect of loop filter bandwidth, DH-PLL frequency synthesizer can perform fast switching speed and low phase noise simultaneously. Under the condition of same hopping speed requirement, DH-PLL can achieve faster switching speed and lower SNR penalty compared with conventional PLL in the OFDM/FH communication system.