• 제목/요약/키워드: Oxide Thickness

검색결과 1,520건 처리시간 0.029초

알루미늄 1050 합금의 양극산화 시간에 따른 산화피막 성장 거동 및 부식 손상 연구 (Growth Behavior and Corrosion Damage of Oxide Film According to Anodizing Time of Aluminum 1050 Alloy)

  • 최예지;정찬영
    • Corrosion Science and Technology
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    • 제21권4호
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    • pp.282-289
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    • 2022
  • Aluminum 1000 series alloy, a pure aluminum with excellent workability and weldability, is mainly used in the ship field. Aluminum alloy can combine with oxygen in the atmosphere and form a natural oxide film with high corrosion resistance. However, its corrosion resistance and durability are decreased when it is exposed to a harsh environment for a long period of time. For solving this problem, a porous oxide film can be formed on the surface using an anodizing treatment method, a typical surface technique among various methods. In this study, aluminum 1050 alloy was anodized for 2 minutes, 6 minutes, and 10 minutes. The structure and shape of the oxide film were then analyzed to determine the corrosion resistance according to the thickness of the oxide film that changed depending on working condition using 15 wt% NaCl. After it was immersed in NaCl solution for 1, 5, and 10 days, corrosion damage was observed. Results confirmed that the thickness of the oxide film increased as the anodization time became longer. The depth of surface damage due to corrosion became deeper when the film was immersed in the 15 wt% NaCl solution for a longer period of time.

Main gate와 side gate 산화층 두께에 따른 DC MOSFET의 전기적 특성에 관한 연구 (A study on electrical characteristics by the oxide layer thickness of main gate and side gate)

  • 나영일;고석웅;정학기;이재형
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2004년도 춘계종합학술대회
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    • pp.658-660
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    • 2004
  • 본 논문에서는 DG MOSFET의 main gate와 side gate사이의 산화층 두께, 그리고 main gate와 Si 기판 사이의 산화층 두께를 변화시킴으로써 전기적 특성을 조사하였다. Main gate와 side gate사이의 간화층 두께가 4nm이고 main gate와 Si 기판사이의 산화층 두께가 3nm일 때 최적의 전기적 특성을 보였다. 이때, side gate 전압은 3V, 그리고 drain 전압은 1.5V를 인가하였다. 결과적으로 DG MOSFET의 전기적 특성은 main gate와 side gate 사이의 산화층 두께보다 main gate와 Si기판사이의 산화층 두께가 중요함을 알았다.

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IGZO, ZnO, AZO OMO 구조의 Ag두께 변화에 따른 투과율과 에너지 밴드 갭의 변화 (Change in the Energy Band Gap and Transmittance IGZO, ZnO, AZO OMO Structure According to Ag Thickness)

  • 이승민;김홍배;이상렬
    • 한국전기전자재료학회논문지
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    • 제28권3호
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    • pp.185-190
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    • 2015
  • In this study, we fabricated the indium gallium zinc oxide (IGZO), zinc oxide (ZnO), aluminum zinc oxide (AZO). oxide and silver are deposited by magnetron sputtering and thermal evaporator, respectively transparency and energy bandgap were changed by the thickness of silver layer. To fabricate metal oxide metal (OMO) structure, IGZO sputtered on a corning 1,737 glass substrate was used as bottom oxide material and then silver was evaporated on the IGZO layer, finally IGZO was sputtered on the silver layer we get the final OMO structure. The radio-frequency power of the target was fixed at 30 W. The chamber pressure was set to $6.0{\times}10^{-3}$ Torr, and the gas ratio of Ar was fixed at 25 sccm. The silver thickness are varied from 3 to 15 nm. The OMO thin films was analyzed using XRD. XRD shows broad peak which clearly indicates amorphous phase. ZnO, AZO, OMO show the peak [002] direction at $34^{\circ}$. This indicate that ZnO, AZO OMO structure show the crystalline peak. Average transmittance of visible region was over 75%, while that of infrared region was under 20%. Energy band gap of OMO layer was increased with increasing thickness of Ag layer. As a result total transmittance was decreased.

가우스 함수의 파라미터에 따른 비대칭형 무접합 이중 게이트 MOSFET의 문턱전압 이하 스윙 분석 (Analysis on Subthreshold Swing of Asymmetric Junctionless Double Gate MOSFET for Parameters for Gaussian Function)

  • 정학기
    • 한국전기전자재료학회논문지
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    • 제35권3호
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    • pp.255-263
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    • 2022
  • The subthreshold swing (SS) of an asymmetric junctionless double gate (AJLDG) MOSFET is analyzed by the use of Gaussian function. In the asymmetric structure, the thickness of the top/bottom oxide film and the flat-band voltages of top gate (Vfbf) and bottom gate (Vfbb) could be made differently, so the change in the SS for these factors is analyzed with the projected range and standard projected deviation which are parameters for the Gaussian function. An analytical subthreshold swing model is presented from the Poisson's equation, and it is shown that this model is in a good agreement with the numerical model. As a result, the SS changes linearly according to the geometric mean of the top and bottom oxide film thicknesses, and if the projected range is less than half of the silicon thickness, the SS decreases as the top gate oxide film is smaller. Conversely, if the projected range is bigger than a half of the silicon thickness, the SS decreases as the bottom gate oxide film is smaller. In addition, the SS decreases as Vfbb-Vfbf increases when the projected range is near the top gate, and the SS decreases as Vfbb-Vfbf decreases when the projected range is near the bottom gate. It is necessary that one should pay attention to the selection of the top/bottom oxide thickness and the gate metal in order to reduce the SS when designing an AJLDG MOSFET.

텅스텐 할로겐 램프를 사용하는 ZMR공정의 매개변수 최적화에 관한 연구 (A Study on Optimization of Process Parameters in Zone Melting Recrystallization Using Tungsten Halogen Lamp)

  • 최진호;송호준;이호준;김충기
    • 한국재료학회지
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    • 제2권3호
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    • pp.180-190
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    • 1992
  • ZMR공정에서 발생하기 쉬운 폴리실리콘의 엉김현상(agglomeration), 슬림, 그리고 실리콘기판이 국부적으로 녹는 현상 등을 방지하기 위한 방법과 재결정화된 박막의 질을 향상시키기 위하여 폴리실리콘과 보호 산화막(capping oxide)두계를 변화시킨 실험 결과를 서술한다. 폴리실리콘의 엉김현상은 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막(buried oxide)의 계면에서의 wetting각과 관계되는데, 엉김현상을 방지하기 위해서는 암모니아 가스 분위기에서 $1100^{\circ}$C, 3시간 동안 열처리하여 폴리실리콘과 보호 산화막 그리고 폴리실리콘과 매몰 산화막의 계면에 질소를 주입시키면 된다. 실리콘 기판의 뒷면이 국부적으로 녹아 SOI구조가 파괴되는 현상과 슬립은 실리콘 기판의 뒷면을 모래타격(sandblast)하여 약 $20{\mu}m$의 거칠기를 가지도록 했을때 방지할 수 있었다. 재결정화된 폴리실리콘의 두께가 두꺼워짐에 따라 재결정화된 박막에서 subboundary의 간격은 넓어지고, 재결정화된 실리콘 두께의 균일성은 보호 산화막이 두꺼울수록 향상된다. 폴리실리콘의 두께를 $1{\mu}m$로 하였을때 subboundary의 간격은 약 $70-120{\mu}m$정도였고 폴리실리콘의 두께가 $1{\mu}m$이고 보호산화막의 두께가 $2.5{\mu}m$일때, 재결정화 후 실리콘의 두게 균일도는 약 ${\pm}200{\AA}$정도였다.

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비대칭 DGMOSFET의 상하단 산화막 두께비에 따른 터널링 전류 분석 (Analysis of Tunneling Current of Asymmetric Double Gate MOSFET for Ratio of Top and Bottom Gate Oxide Film Thickness)

  • 정학기
    • 한국정보통신학회논문지
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    • 제20권5호
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    • pp.992-997
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    • 2016
  • 본 논문에서는 단채널 비대칭 이중게이트 MOSFET의 상하단 산화막 두께비에 대한 터널링 전류의 변화에 대하여 분석하고자 한다. 채널길이가 5 nm까지 감소하면 차단전류에서 터널링 전류의 비율이 크게 증가하게 된다. 이와 같은 단채널효과는 상하단 게이트 산화막 구조를 달리 제작할 수 있는 비대칭 이중게이트 MOSFET에서도 발생하고 있다. 본 논문에서는 상하단 게이트 산화막 두께비 변화에 대하여 차단전류 중에 터널링 전류의 비율 변화를 채널길이, 채널두께, 도핑농도 및 상하단 게이트 전압을 파라미터로 계산함으로써 단채널에서 발생하는 터널링 전류의 영향을 관찰하고자 한다. 이를 위하여 포아송방정식으로부터 해석학적 전위분포를 구하였으며 WKB(Wentzel-Kramers-Brillouin)근사를 이용하여 터널링 전류를 구하였다. 결과적으로 단채널 비대칭 이중게이트 MOSFET에서는 상하단 산화막 두께비에 의하여 터널링 전류가 크게 변화하는 것을 알 수 있었다. 특히 채널길이, 채널두께, 도핑농도 및 상하단 게이트 전압 등의 파라미터에 따라 매우 큰 변화를 보이고 있었다.

산화막을 입힌 지르코늄 합금의 수소화 반응에 관한 연구 (A Study on the Hydriding Reaction of Pre-oxidized Zr Alloys)

  • 김선기;방제건;김대호;임익성;양용식;송근우
    • 한국세라믹학회지
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    • 제47권2호
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    • pp.106-112
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    • 2010
  • This paper presents some experimental results on incubation time for massive hydriding of Zr alloys with oxide thickness. Oxide effects experiments on massive hydriding reaction of commercial Zr alloy claddings and pre-oxidized Zr alloys with hydrogen gas were carried out in the temperature range from 300 to $400^{\circ}C$ with thermo-gravimetric apparatus. Experimental results for oxide effects on massive hydriding kinetics show that incubation time is not proportional to oxide thickness and that the massive hydriding kinetics of pre-filmed Zr alloys follows linear kinetic law and the hydriding rate are similar to that of oxide-free Zr alloys once massive hydriding is initiated. There was a difference in micro-structures between oxide during incubation time and oxide after incubation time. Physical defects such as micro-cracks and pores were observed in only oxide after incubation time. Therefore, the massive hydriding of Zr alloys seems to be ascribed to short circuit path, mechacical or physical defects, such as micro-cracks and pores in the oxide rather than hydrogen diffusion through the oxide resulting from the increase of oxygen vacancies in the hypostoichiometric oxide.

5V-Programmable E$^2$PROM을 위한 비휘발성 MONOS 기억소자의 Scale-down (scale-down of the Nonvolatile MONOS Memory Devices for the 5V-Programmable E$^2$PROM)

  • 이상배;이상은;김선주;서광열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 추계학술대회 논문집
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    • pp.33-36
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    • 1994
  • The characteristics of the nonvolatile MONOS memory devices as the nitride thickness is scaled down while maintaining constant tunneling oxide thickness and blocking oxide thickness have been investigated in order to obtain the 5V-programmable E$^2$PROM. We have found that 1V memory window for a 5V programming voltage and 10 year data retention can be achieved in the scaled MONOS memory devices with a 50 blocking oxide, a 57 nitride and a 19 tunneling oxide.

As Ion 주입된 Si 기판위의 native oxide가 RTP법으로 성장시킨 Ti-Silicides의 형성에 미치는 영향 (Effects of native oxide on Si substrates-As ion implanted on the formation of Ti-Silicides grown by RTP method)

  • 정주혁;최진석;백수현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.319-323
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    • 1988
  • For finding the effects of As on $TiSi_2$ formation, sputter deposited Ti film on Si substrates implanted with various doses of As have been rapid thermal annealed in Ar atmosphere at temperatures of 600-900$^{\circ}C$ for 20 sec. The sheet resistance of Ti-Silicides was examined with 4-point probe, the thickness with ${\alpha}$-step, and the As dopant behavior in Si substrates with ASR. The thickness of Ti-Silicides decreased with increasing As doping, but Ti-Silicides sheet resistance increased with increasing it. However, the critical concentration effect reported by Park et al. was not observed. We observed that the thickness of native oxide increase with increasing As doping. Thus, we concluded that native oxide act as a "barrier" for the Si diffusion.

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Oxide-Nitride-Oxide막을 게이트 절연막으로 사용하여 제조한 다결정실리콘 박막트랜지스티의 특성 (Properties of Poly-Si TFT's using Oxide-Nitride-Oxide Films as Gate Insulators)

  • 이인찬;마대영
    • 한국전기전자재료학회논문지
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    • 제16권12호
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    • pp.1065-1070
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    • 2003
  • HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.