• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.82-87
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• 2019

One of the most critical aspects of the semiconductor industry is the quality of the wafer surface. And the vibrations of wafer grinder are supposed to be the most dominant factors to damage the wafer surface quality. In this study, structure of a wafer grinder has been analyzed through experiments and computer simulations to figure out the main reasons of the vibrations. And the design alterations based on the analysis were applied to identify the effects of those alterations on the vibration suppression. The result shows that the design alterations can effectively suppress about 90% of the vibrations.

• Proceedings of the Korean Society of Computer Information Conference
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• 2015.01a
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• pp.297-298
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• 2015

반도체 제조 및 FPD제조 공정 중 WAFER 및 GLASS 제품의 상태를 직접적으로 관리하는 기술로서 기존에 널리 사용하고 있는 방법은 CHAMBER의 온도나 상태 등의 설비 컨디션 상태를 관리 모니터링 하는 것이다. 반도체 제조의 공정비용을 최소화하기 위하여 기존 방법과 달리 WAFER 및 GLASS의 온도 상태 등을 직접적으로 모니터링 하는 시스템으로 반도체 FPD제조 공정 중 장비의 개별 특성에 따라 제품의 공정 편차로 인해 발생되는 공정불량을 실시간으로 모니터링함으로서 불량을 최소화 할 수 있는 시스템을 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.421-426
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• 1989

Many of semiconductor manufacturing companies persuit automation of wafer fabrication to improve the yields and quality of their products. Development of real-time control system for wafer fabrication and wafer/cassette automatic transfer-system is the most important part to achieve the purpose. In this paper, SECS protocol proposed by SEMI is briefly reviewed and an implementation method of real-time monitoring and control system is suggested as one of the possible ways for wafer fabrication automation. The system consists of process equipments supporting SECS.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Proceedings of the Korean Society of Computer Information Conference
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• 2015.07a
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• pp.1-4
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• 2015

현재 고해상도 디스플레이 제품 생산은 대량 생산 공정 시스템으로 가동하고 있으며, 대량 생산 과정에서 WAFER의 제작 불량률을 낮추는 것이 생산업체에서 무엇보다도 주요한 목표이며 이와 함께 불량 제품을 정확하고 빠르게 검출하는 것이 매우 중요하다. 본 논문에서는 불량 WAFER을 정확하게 검출하기 위한 검출시스템으로 멀티 포인트 온도 검출 방법으로 구현된 면적형 온도 센서 기능과 검출된 데이터를 유/무선 통신방식으로 상위의 관리/모니터링 시스템으로 전송 할 수 있는 기능을 가진 마스터 콘트롤러 시스템을 제안한다.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1820-1822
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• 2004

In this study, major research fields are classified as ozone generation system for dry cleaning wafer of etched silicon wafer, dry cleaning process of etched silicon wafer which includes SEM analysis and ESCA analysis. The following results are deduced from each experiment and analysis. The magnitudes of carbon and silicon were similar to the survey spectrum of silicon wafer which does not cleaning, but magnitude of oxygen was much bigger Because UV light activates oxygen molecules in the oxide film on the silicon wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.