• Proceedings of the KSME Conference
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.372.2-372.2
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• 2016

Various nanobiosensors have been developed and extensively investigated. For their practical applications, however, the reproducibility and uniformity should be good enough and the mass-production should be possible. To fabricate anodized aluminium oxide (AAO)-based nanobiosesnor on wafer scale, we have designed and constructed a wafer-scale anodizing system. $1{\mu}m$-thick-aluminum is deposited on 4 inch SiO2/Si substrate and then anodized, resulting in uniform nanopores with an average pore diameter of about 65 nm. Furthermore, most AAO sensors constructed on this wafer provide capacitance values of 30 nF ~ 60 nF in PBS, demonstrating their uniformity.

• IE interfaces
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• 제16권3호
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• pp.344-351
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• 2003

Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• 제12권3호
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• pp.120-125
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• 2002

Si-wafers for solar cells were cast in a size of $50{\times}46{\times}0.5{\textrm}{mm}^3$ by vacuum casting method. The graphite mold coated by BN powder, which was to prevent the reaction of carbon with the molten silicon, was used. Without coating, the wetting and reaction of Si melt to graphite mold was very severe. In the case of BN coating, SiC was formed in the shape of tiny islands at the surface of Si wafer by the reaction between Si-melt and carbon of the graphite mold on the high temperature. The grain size was about 1 mm. The efficiency of Si solar cell was lower than that of Si solar cell fabricated on commercial single and poly crystalline Si wafer. The reason of low efficiency was discussed.

• Journal of the Korean institute of surface engineering
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• 제29권5호
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• pp.482-486
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• 1996

The progress of microelectronics technology has been requiring agressive developments of device technologies. Also the requirements of the next generation devices is heading to the limits of their functions and materials, and hence asking the very specific silicon wafer such as SOI(Silicon On Insulator) wafer. The talk covers the dome stic and world-wide status of SOI device developments and applications. The presentation will also touch some predictions such as SOI device prgress schedules, impacts on the normal wafer developments, market sizes, SOI wafer prices, and so on. Finally it will cover technical aspects which are silicon oxide conditions for bonding, point defects and, surface contaminations. These points will be hopefully overcome by involved people in microelectronics industry.

• Journal of Sensor Science and Technology
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• 제28권3호
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• pp.152-156
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• 2019

An ultraviolet (UV) image sensor is an extremely important optoelectronic device used in scientific and medical applications because it can detect images that cannot be obtained using visible or infrared image sensors. Because photodetectors and transistors are based on different materials, conventional UV imaging devices, which have a hybrid-type structure, require additional complex processes such as a backside etching of a GaN epi-wafer and a wafer-to-wafer bonding for the fabrication of the image sensors. In this study, we developed a monolithic GaN UV passive pixel sensor (PPS) by integrating a GaN-based Schottky-barrier type transistor and a GaN UV photodetector on a wafer. Both individual devices show good electrical and photoresponse characteristics, and the fabricated UV PPS was successfully operated under UV irradiation conditions with a high on/off extinction ratio of as high as $10^3$. This integration technique of a single pixel sensor will be a breakthrough for the development of GaN-based optoelectronic integrated circuits.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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• pp.99.2-99.2
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafer and surface morphology. It is observed that passivation quality of a-Si:H thin-films on c-Si wafer highly depends on wafer surface conditions. The MCLT(Minority carrier life time) of wafer incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with cleaning process and surface morpholgy. By applying improved cleaning processes and surface morphology we can obtain the MCLT of $200{\mu}sec$ after H-termination and above 1.5msec after i a-Si:H thin film deposition, which has implied open circuit voltage of 0.720V.

• Journal of the Microelectronics and Packaging Society
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• 제21권4호
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• pp.63-68
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• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.

• Transactions of the Korean Society of Mechanical Engineers A
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• 제29권9호
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• pp.1169-1174
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• 2005

Imprint lithography is a promising method for high-resolution and high-throughput lithography using low-cost equipment. In particular, ultraviolet-nanoimprint lithography (UV-NIL) is applicable to large area imprint easily. We have proposed a new UV-NIL process using an elementwise patterned stamp (EPS), which consists of a number of elements, each of which is separated by channel. Experiments on UV-NIL are performed on an EVG620-NIL using the EPS with 3mm channel width. The replication of uniform sub 70 nm lines using the EPS is demonstrated. We investigate the nonuniformity of residual layer caused by wafer deformation in experiment with varying wafer thickness. Severely deformed wafer works as an obstacle in spreading of dropped resin, which causes nonuniformity of thickness of residual layer. Numerical simulations are conducted to analyze aforementioned phenomenon. Wafer deformation in the process is simulated by using a simplified model, which is a good agreement with experiments.

• Journal of the Korean Crystal Growth and Crystal Technology
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• 제26권3호
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• pp.121-125
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• 2016

The effect of temperature and pressure in the nitrogen ambient furnace on bulk micro defect (BMD) and denuded zone (Dz) is experimentally investigated. It is found that as pressure increases, Dz depth increases with a small decrease of BMD density in the range of temperature, $100{\sim}300^{\circ}C$. BMD density with hot isostatic pressure treatment (HIP) at temperature of $850^{\circ}C$ is higher than that without HIP while Dz depth is lower due to much higher BMD density. As the pressure increases, BMD density is increased and saturated to a critical value, and Dz depth increases even if BMD density is saturated. The concentration of nitrogen increases near the surface with increasing pressure, and the peak of the concentration moves closer to the surface. The nitrogen is gathered near the surface, and does not become in-diffusion to the bulk of the wafer. The silicon nitride layer near the surface prevents to inject the additional nitrogen into the bulk of the wafer across the layer. The nitrogen does not affect the formation of BMD. On the other hand, the oxygen is moved into the bulk of the wafer by increasing pressure. Dz depth from the surface is extended into the bulk because the nuclei of BMD move into the bulk of the wafer.