• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.98-107
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• 1996

In this paper, we propose a scheme that maps the time-delay neural network (TDNN) into the neurocomputer called EMIND-II which has the wavefront toroidal mesh-array structure. This neurocomputer is scalable, consists of many timeshared virtual neurons, is equipped with programmable on-chip learning, and is versatile for building many types of neural networks. Also we define the programming model of this array and derive the parallel algorithms about TDNN for the proposed neurocomputer EMIND-II. In addition, the computational complexities for the parallel and serial algorithms are compared. Finally, we introduce an application of this neurocomputer to word recognition.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.959-962
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• 2009

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, GSM, and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System on Chip) technology, thus a noble modem design proper for SoC technology is necessary. As those systems shall be operated at different frequency band with only a single terminal, a problem that a nonlinear characteristic according to the system and its frequency band is occurred. In this paper a noble modem design for multi-core systems is proposed and the nonlinear characteristics for those systems is analysed. The proposed modem design is based on OFDM(Orthogonal Frequency Division Multiplexing) and MC-CDMA scheme. And nonlinear characteristic analysis is done by PSD measurement.

• Electronics and Telecommunications Trends
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• v.9 no.1
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• pp.75-80
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• 1994

신경회로망을 아날로그 VLSI로 구현하는 것은 디지털 구현방법에 비하여 집적도와 신호처리 속도의 장점이 있는 반면에 아날로그 신호의 저장 방법, 시냅스를 구현한 곱셈기의 비선형성, 동작영역, zero offset, noise, gain의 변동등의 문제가 존재한다. 여기서는, 이러한 문제들이 신경회로망을 구현한 아날로그 회로에서 어떤 형태로 나타나는지 알아보았다. 위와 같은 비이상적 요인들이 신경회로망의 성능에 미치는 영향이 파악되면 보다 더 신뢰성을 갖는 신경회로망 chip을 설계/제작할 수 있을 것이다.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.76-84
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• 2020

Neuromorphic hardware refers to brain-inspired computers or components that model an artificial neural network comprising densely connected parallel neurons and synapses. The major element in the widespread deployment of neural networks in embedded devices are efficient architecture for neuromorphic hardware with regard to performance, power consumption, and chip area. Spiking neural networks (SiNNs) are brain-inspired in which the communication among neurons is modeled in the form of spikes. Owing to brainlike operating modes, SNNs can be power efficient. However, issues still exist with research and actual application of SNNs. In this issue, we focus on the technology development cases and market trends of two typical tracks, which are listed above, from the point of view of artificial intelligence neuromorphic circuits and subsequently describe their future development prospects.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.5-8
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• 1999

In this paper, we suggest a way of implementing ISDN S-Interface through two-wire premises telephone networks instead of using four wires as in the existing ISDN systems. This will help many developing or underdeveloped countries in the world to introduce ISDN services, where they have only two or low wires as in-building telephone networks. We suggest new physical-layer specifications for two-wire S-interface similar to that in ITU-T recommendations I.430 for four-wire systems, design a tranceiver according to the suggested specifications, and implement it using an FPGA We build a test board with the chip on it and succeed in connecting to Internet.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.2974-2976
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• 1999

본 논문에서는 단일패턴과 다중패턴 학습이 가능한 FNNs(Feedforward Neural Networks)을 하드웨어로 구현하는데 필요한 학습방안을 제안한다. 제안된 학습방안은 기존의 하드웨어 구현에 이용되는 방식과는 전혀 다른 방식이며, 오히려 기존의 소프트웨어 학습방식과 유사하다. 기존의 하드웨어 구현에서 사용되는 방법은 오프라인 학습이나 단일패턴 온 칩(on-chip) 학습방식인데 반해, 제안된 학습방식은 단일/다중패턴은 칩 학습방식으로 다층 FNNs 회로와 학습회로 사이에 스위칭 회로를 넣어 구현되었으며, FNNs의 학습회로는 선형 시냅스 회로와 선형 곱셈기 회로를 사용하여MEBP(Modified Error Back-Propagation) 학습규칙을 구현하였다. 제안된 방식은 기존의 CMOS 공정으로 구현되었고 HSPICE 회로 시뮬레이터로 그 동작을 검증하였다 구현된 FNNs은 어떤 학습패턴 쌍에 의해 유일하게 결정되는 출력 전압을 생성한다. 제안된 학습방안은 향후 학습 가능한 대용량 신경망의 구현에 매우 적합하리라 예상된다.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2000.11a
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• pp.59-60
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• 2000

The past few years have seen a dramatic increase in gene expression data on the basis of DNA microarrays or DNA chips. Going beyond a generic view on the genome, microarray data are able to distinguish between gene populations in different tissues of the same organism and in different states of cells belonging to the same tissue. This affords a cell-wide view of the metabolic and regulatory processes under different conditions, building an effective basis for new diagnoses and therapies of diseases. In this talk we present machine learning techniques for effective mining of DNA microarray data. A brief introduction to the research field of machine learning from the computer science and artificial intelligence point of view is followed by a review of recently-developed learning algorithms applied to the analysis of DNA chip gene expression data. Emphasis is put on graphical models, such as Bayesian networks, latent variable models, and generative topographic mapping. Finally, we report on our own results of applying these learning methods to two important problems: the identification of cell cycle-regulated genes and the discovery of cancer classes by gene expression monitoring. The data sets are provided by the competition CAMDA-2000, the Critical Assessment of Techniques for Microarray Data Mining.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.213-219
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• 2010

Recently, a multi-core system is studied for single terminal's operations on various service networks for mobile systems. Therefore, it is expected that mobile systems capable of supporting WCDMA, MC-CDMA, CDMA and WiBro would be developed. Mobile systems for supporting various service networks is able to be implemented on a single chipset via SoC(System one Chip) technology, thus a noble modem design proper for SoC technology is necessary. For high speed data transmission of 4G mobile communication services, OFDM scheme has to be applied. But, an OFDM signal consists of a number of independently modulated subcarriers, and superposition of these subcarriers cause a problem that can give a large PAPR. In this paper, a noble modem design for 4G mobile communication services and PAPR reduction method for solving the PAPR problem are proposed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.6
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• pp.1242-1249
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• 2012

This paper proposes a metastability-free synchronization method and a mesochronous synchronizer for NoC. It uses the clock transmitted from TX as a strobe and solves the metastability problem by selecting one of rising or falling clock edge depending on the sampling value in RX when the phase difference between clocks is under a metastability window. The logic simulation results show that it works without metastability under $0^{\circ}{\sim}360^{\circ}$ phase difference in the synchronizer that a fault is inserted. The mesochronous synchronizer has a simple control logic and is suitable for NoC.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.251-262
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• 2019

In this paper, we propose a simulator that provides various algorithms of RBF networks on neuromorphic chips. To develop algorithms based on neuromorphic chips, the disadvantages of using simulators are that it is difficult to test various types of algorithms, although time is fast. This proposed simulator can simulate four times more types of network architecture than existing simulators, and it provides an additional a two-layer structure algorithm in particular, unlike RBF networks provided by existing simulators. This two-layer architecture algorithm is configured to be utilized for multiple input data and compared to the existing RBF for performance analysis and validation of utilization. The analysis showed that the two-layer structure algorithm was more accurate than the existing RBF networks.