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Development of a Simulator for RBF-Based Networks on Neuromorphic Chips

뉴로모픽 칩에서 운영되는 RBF 기반 네트워크 학습을 위한 시뮬레이터 개발

  • 이여울 (고려대학교 컴퓨터정보학과) ;
  • 서경은 (고려대학교 컴퓨터정보학과) ;
  • 최대웅 (고려대학교 컴퓨터정보학과) ;
  • 고재진 (전자부품연구원 임베디드SW센터) ;
  • 이상엽 (전자부품연구원 임베디드SW센터) ;
  • 이재규 (전자부품연구원 임베디드SW센터) ;
  • 조현중 (고려대학교 컴퓨터융합소프트웨어학과)
  • Received : 2019.04.17
  • Accepted : 2019.07.02
  • Published : 2019.11.30

Abstract

In this paper, we propose a simulator that provides various algorithms of RBF networks on neuromorphic chips. To develop algorithms based on neuromorphic chips, the disadvantages of using simulators are that it is difficult to test various types of algorithms, although time is fast. This proposed simulator can simulate four times more types of network architecture than existing simulators, and it provides an additional a two-layer structure algorithm in particular, unlike RBF networks provided by existing simulators. This two-layer architecture algorithm is configured to be utilized for multiple input data and compared to the existing RBF for performance analysis and validation of utilization. The analysis showed that the two-layer structure algorithm was more accurate than the existing RBF networks.

본 논문에서는 뉴로모픽 칩에서 운영되는 RBF 네트워크를 다양한 형태로 제공하는 시뮬레이터를 제안한다. 뉴로모픽 칩의 RBF 네트워크를 학습할 때 시뮬레이터를 사용할 경우에는 시간은 단축되지만 다양한 형태의 알고리즘을 테스트하기 어렵다는 단점이 있다. 본 제안 시뮬레이터는 기존 시뮬레이터와 비교하여 4배 많은 종류의 네트워크 구조 모의실험이 가능하며 특히, 이중 레이어 구조를 추가로 제공한다. 이중 레이어 구조는 다중 데이터 입력 시 활용되도록 구성하였으며 성능 분석 결과, 본 이중 레이어 구조가 기존보다 더 높은 정확도를 보였다.

Keywords

Acknowledgement

Grant : 저전력 독립운용이 가능한 내장형 인공지능 모듈 및 내비게이션 응용 서비스 기술 개발

Supported by : 산업통산부

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