• Journal of Sensor Science and Technology
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• v.13 no.2
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• pp.101-109
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• 2004

This paper presents a novel z-axis accelerometer with perfectly aligned vertical combs fabricated using the extended sacrificial bulk micromachining (extended SBM) process. The z-axis accelerometer is fabricated using only one (111) SOI wafer and two photo masks without wafer bonding or CMP processes as used by other research efforts that involve vertical combs. In our process, there is no misalignment in lateral gap between the upper and lower comb electrodes, because all critical dimensions including lateral gaps are defined using only one mask. The fabricated accelerometer has the structure thickness of $30{\mu}m$, the vertical offset of $12{\mu}m$, and lateral gap between electrodes of $4{\mu}m$. Torsional springs and asymmetric proof mass produce a vertical displacement when an external z-axis acceleration is applied, and capacitance change due to the vertical displacement of the comb is detected by charge-to-voltage converter. The signal-to-noise ratio of the modulated and demodulated output signal is 80 dB and 76.5 dB, respectively. The noise equivalent input acceleration resolution of the modulated and demodulated output signal is calculated to be $500{\mu}g$ and $748{\mu}g$. The scale factor and linearity of the accelerometer are measured to be 1.1 mV/g and 1.18% FSO, respectively.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.59-66
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• 2005

CMOS LC VCO for tri-bind wireless LAN applications was designed in 1.8V 0.18$\mu$m CMOS process. PMOS transistors were chosen for VCO core to reduce flicker noise. The possible operation was verified for 5.8GHz band (5.725$\~$5.825GHz), 5.2GHz band (5.150$\~$5.325GHz), and 2.4GHz band (2.412$\~$2.484GHz) using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing technique was used for capacitance linearization and PLL stability improvement. VCO core consumed 2mA current and $570{\mu}m{\times}600{\mu}m$ die area. The phase noise was lower than -110dBc/Hz at 1MHz offset for tri-band frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.964-969
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• 2007

A regulated low phase noise differential colpitts VCO(Voltage Controlled Oscillator) for mobile RFID system is presented. The differential colpitts VCO meets the dense reader environment specifications. The VCO use a $0.35{\mu}m$ technology and achieves tuning range $1.55{sim}2.053 GHz$. Measuring 910 MHz frequency divider output, phase noise performance is -106 dBcMz and -135dBc/Hz at 40 kHz and 1MHz offset, respectively. 5-bit digital coarse-tuning and accumulation type MOS varactors allow for 28.2% tuning range, which is required to cover the LO frequency range of a UHF Mobile RFID system, Optimum design techniques ensure low VCO gain(<45 MHz/V) for good interoperability with the frequency synthesizer. To the author' knowledge, this differential colpitts VCO achieves a figure of merit(FOM) of 1.93dB at 2-GHz band.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• 한국신재생에너지학회:학술대회논문집
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• 2011.11a
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• pp.100-100
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• 2011

Nanomaterial architecture with highly ordered, vertically oriented $TiO_2$ nanotube arrays shows a good promise for diverse technological applications. As inspired from the literature reports that Nickel modification can improve the photocatalytic activity of $TiO_2$, it was planned to coat Ni into the $TiO_2$ matrix. In this study, first $TiO_2$ nanotubes(TiNTs) were prepared by anodization (60V,3min) in HF-free aqueous electrolyte on ultrasonically cleaned polished titanium sheet substrates ($1{\times}7cm^2$). The typical thickness of the sintered TiNT ($500^{\circ}C$for10min) was ~1 micronas confirmed from the FESEM study. In the next part, as-anodized and sintered TiNT/Ti photoanodes were used to coat Ni by AC electrodeposition from aqueous 0.1M nickel sulphate solution. During AC electrodeposition, conditions such as 1V DC offset voltage, 9V amplitude (peak-to-peak) and 750 Hz frequency were fixed constant and the deposition time was varied as 0.5 min, 1 min, 2 min and 10 min. The photoelectrochemical performance of pristine and Ni modified TiNT/Ti photoanodes was measured in 1N NaOH electrolyte under 1 SUN illumination in the potential range of -1V and 1.2V versus Ag/AgCl reference electrode. The photocurrent performance of TiNT/Ti photoanode decreased upon Ni modification and the results were confirmed after repeated experiments. This suggests us that Ni modification inhibits the photoelectrochemical performance of $TiO_2$ nanotubes.

• Journal of the Korean Society for Railway
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• v.20 no.4
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• pp.448-457
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• 2017

In this paper, for high speed railway propulsion systems, a single phase PWM Converter using discontinuous PWM (DPWM) was investigated. The conventional PWM Converter uses a low frequency modulation index of less than 10 to reduce switching losses due to high power characteristics, which results in low control frequency bandwidth and requires an additional compensation method. To solve these problems, the DPWM method, which is commonly used in three phase PWM Inverters, was adopted to a single phase PWM Converter. The proposed method was easily implemented using offset voltage techniques. Method can improve the control performance by doubling the frequency modulation index for the same switching loss, and can also bring the same dynamic characteristics among switches. Proposed DPWM method was verified by simulation of 100 kW PWM converter.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.401-408
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• 2001

This paper shows the design, fabrication and performance analysis of VCO which plays a major role in 5.8 GHz RF module for ITS. The design specifications of the VCO are determined on the basis of 5.8 GHz RF modul performance requirements. The design parameters are optimized through ADS simulation tool. The operating characteristic and performance analysis of the implemented VCO based on the design parameters are accomplished. The frequency variations according to the voltage change(0 ~5 V) of varactor diode are from 5.42 GHz to 5.518 GHz and the power level is 6.5 dBm. The second harmonic suppression are -21.5 dBc at 5.51 GHz and the phase noise characteristics are -83.81 dBc at 10 kHz offset frequency. The implemented VCO is available to not only DSRC and also, 5.8 GHz other systems.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.114-122
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• 1997

This paper describes the design and development of a smart digital load cell used forweighing installations. Sice the load cell sensor to be used is very sensitive for weight cariation, the load cell must have the temperature stability, low-drift and the high-resolution of the A/D conversion for accuracy. A new analog circuit which is controlled by one chip micro-processer has been developed to reduce the offset voltage and the drift characteristics of operational amplifiers, and has been adapted into the digital load cell. Also, a software algorithm has been developed to obtain the stable and accurate A/D conversion. This software includes a RS-485 communication program to control the digital load cell, which gives a capability of backing-up the calibration data and transferring control data. The simulation and evaluation of the designed digital load cell has been shown as having the good performance. which will give useful application to the weighing installations as a remote weighing sensor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.