JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A 6b 1.2 GS/s 47.8 mW 0.17 mm2 65 nm CMOS ADC for High-Rate WPAN Systems

  • Park, Hye-Lim (Dept. of Electronic Engineering, Sogang University) ;
  • Kwon, Yi-Gi (Dept. of Electronic Engineering, Sogang University) ;
  • Choi, Min-Ho (Dept. of Electronic Engineering, Sogang University) ;
  • Kim, Young-Lok (Dept. of Electronic Engineering, Sogang University) ;
  • Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University) ;
  • Jeon, Young-Deuk (Electronics and Telecommunications Research Institute (ETRI)) ;
  • Kwon, Jong-Kee (Electronics and Telecommunications Research Institute (ETRI))
  • Received : 2011.03.24
  • Published : 2011.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

Keywords

References

  1. S. C. Lee, Y. D. Jeon, K. D. Kim, J. K. Kwon, J. D. Kim, J. W. Moon, and W. Y. Lee, "A 10-b 205-MS/s 1.0-mm2 90-nm CMOS pipeline ADC for flat panel display applications," IEEE J. Solid-State Circuits, Vol.42, No.12, pp.2688-2695, Dec., 2007. https://doi.org/10.1109/JSSC.2007.908760
  2. J. S. Lee, J. H. Bae, H. Y. Kim, J. Y. Um, J. Y. Sim, and H. J. Park, "A design guide of 3-stage CMOS operational amplifier with nested Gm-C frequency compensation," Journal of Semiconductor Technology and Science, Vol.7, No.1, pp.20-27, Mar., 2007. https://doi.org/10.5573/JSTS.2007.7.1.020
  3. K. Uyttenhove and M. S. J. Steyaert, "Speed-power-accuracy tradeoff in high-speed CMOS ADCs," IEEE Trans. Circuits Syst. II, Vol.49, No.4, pp.280-287, Apr., 2002. https://doi.org/10.1109/TCSII.2002.801191
  4. C. Y. Chen, M. Le, and K. Y. Kim, "A low power 6-bit flash ADC with reference voltage and commonmode calibration," IEEE J. Solid-State Circuits, Vol. 44, No.4, pp.1041-1046, Dec., 2009. https://doi.org/10.1109/JSSC.2009.2014701
  5. J. He, S. Zhan, D. Chen, and R. L. Geiger, "Analyses of static and dynamic random offset voltages in dynamic comparators," IEEE Trans. Circuits Syst. I, Vol.56, No.5, pp.911-919, May, 2009. https://doi.org/10.1109/TCSI.2009.2015207
  6. M. Kijima, K. Ito, K. Kamei, and S. Tsukamoto, "A 6b 3GS/s flash ADC with background calibration," Proc. CICC, pp.283-286, Sept., 2009.
  7. Z. Cao, S. Yan, and Y. Li, "A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 um CMOS," IEEE J. Solid-State Circuits, Vol.44, No.3, pp.862-873, Mar., 2009. https://doi.org/10.1109/JSSC.2008.2012329
  8. E. Alpman, H. Lakdawala, and L. R. Carley, "A 1.1 V 50 mW 2.5 GS/s 7b time-interleaved C-2C SAR ADC in 45 nm LP digital CMOS," ISSCC Dig. Tech. Papers, pp.76-77, Feb., 2009.
  9. J. Yang, T. L. Naing, and B. Brodersen, "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS," Proc. CICC, pp.287-290, Sept., 2009.
  10. M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-um CMOS," IEEE J. Solid-State Circuits, Vol.36, No.12, pp.1847-1858, Dec., 2001. https://doi.org/10.1109/4.972135
  11. S. H. Lee, J. W. Moon, and S. H. Lee, "An 8 b 52 MHz double-channel CMOS subranging A/D converter for DSL applications," IEICE Trans. Electron., Vol.E84-C, No.4, pp.470-474, Apr., 2001.
  12. K. Uyttenhove and M. S. J. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-um CMOS," IEEE J. Solid-State Circuits, Vol.38, No.7, pp.1115-1122, Jul., 2003. https://doi.org/10.1109/JSSC.2003.813244
  13. C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, "A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-um Digital CMOS," IEEE J. Solid-State Circuits, Vol.40, No.7, pp.1499-1505, Jul., 2005. https://doi.org/10.1109/JSSC.2005.847215
  14. G. Geelen, "A 6b 1.1 GSample/s CMOS A/D converter," ISSCC Dig. Tech. Papers, pp.128-129, Feb., 2001.
  15. Y. J. Kim, J. H. Lee, J. H. Koo, K. H. Baek, and S. Kim, "6-bit 1.6 GS/s 85-mW flash analog to digital converter using symmetric three-input comparator," IEICE Trans. Electron., Vol.E91-C, No.3, pp.392-395, Mar., 2008. https://doi.org/10.1093/ietele/e91-c.3.392
  16. C. K. Hung, J. F. Shiu, I. C. Chen and H. S. Chen, "A 6-bit 1.6 GS/s flash ADC in 0.18-um CMOS with reversed-reference dummy," Proc. ASSCC, pp.335-338, Nov., 2006.
  17. H. Y. Lee, Y. S. You, H. J. Park, J. H. Bae, and Y. C. Jang, "Bubble error rejecter in data converter," U.S. Patent 7,327,292, Feb., 2008.

Cited by

  1. Millimeter-Wave Cellular Wireless Networks: Potentials and Challenges vol.102, pp.3, 2014, https://doi.org/10.1109/JPROC.2014.2299397
  2. A Mismatch-Insensitive 12b 60MS/s 0.18um CMOS Flash-SAR ADC vol.53, pp.7, 2016, https://doi.org/10.5573/ieie.2016.53.7.017