• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.201-210
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• 2002

This paper describes a 3.3 (V) low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS($\upsilon$MOS) down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6(MHz) and a power dissipation of 24.5 (mW) with a single power supply of 3.3 (V) for a CMOS 0.35${\mu}{\textrm}{m}$ n-well technology.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.135-143
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• 2003

This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1292-1295
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• 2002

The performance of the LSI improved drastically due to the progress of the semiconductor manufacturing technology in recent years. However, a new problem such as wiring delay and complication inside the LSI occurs. The study to solve these problems with much research organization is been doing. We tried to solve of these problems by using the neuron MOS transistor with 4-valued signal in addition to the binary signal. In this paper, We present, method which realizes 4-valued logic function. And, a designed circuit, is verified by using HSPICE.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.131-139
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• 1996

This paper describes the chaotic neuron model to represent the complicated states of brain and analyzes the dynamical responses of chaotic neuron such as periodic, bifurcation, and chaotic phenomena which are simulated iwth numerical analysis. Next, the chaotic neuron circuit is implemented w ith the analog electronic devices. The transfer function of chaotic neuron is given by summed the linear and nonlinear property. The output function of chaojtic neuron is designed iwth the two cMOS inverters and a feedback resistor. By adjusting the external voltage, the various dynamical properties are demonstrated. In addition, we construt the chaotic neural networks which are composed of the interconnection of chaotic neuroncircuit such as serial, paralle, and layer connection. On the board experiment, we proved the dynamci and chaotic responses which exist in the human brain.

• Proceedings of the KIEE Conference
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• 1991.11a
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• pp.189-192
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• 1991

This paper presents a modular structure design of analog Hopfield neural network. Each multiplier consists of four MOS transistors which are connected to an op-amp at the front end of a neuron. A pair of MOS transistor is used in order to maintain linear operation of the synapse and can produce positive or negative synaptic weight. This architecture can be expandable to any size neural network by forming tree structure. By altering the connections, other nework paradigms can also be implemented using this basic modules. The stength of this approach is the expandability and the general applicability. The layout design of a four-neuron fully connected feedback neural network is presented and is simulated using SPICE. The network shows correct retrival of distorted patterns.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.191-194
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• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.