• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.

• ETRI Journal
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• v.45 no.5
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.1
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• pp.1-7
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• 2007

In this paper, two kinds of initial oxidation methods i.e., SLTO(Slow Low Temperature Oxidation: $700^{\circ}C$) and RTO(Rapid Thermal Oxidation: $850^{\circ}C$) are applied prior to the plasma nitridation for ultra thin oxide of RPNO (Remote Plasma Nitrided Oxide). It is observed that SLTO has superior characteristics to RTO such as lower SS(Sub-threshold Slope) and improved Ion-Ioff characteristics. Low frequency noise characteristics of SLTO also showed better than RTO both in linear and saturation regime. It is shown that flicker noise is dominated by carrier number fluctuation in the channel region. Therefore, SLTO is promising for nano-scale CMOS technology with ultra thin gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.440-443
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• 2010

We report a top-down approach based on atomic force microscopy (AFM) local anodic oxidation for the fabrication of the nano-pattern field effect transistors (FETs). AFM anodic oxidation is relatively a simple process in atmosphere at room temperature but it still can result in patterns with a high spatial resolution, and compatibility with conventional silicon CMOS process. In this work, we study nano-pattern FETs for various cross-bar distance value D, from ${\sim}0.5\;{\mu}m$ to $1\;{\mu}m$. We compare the optical characteristics of the patterned FETs and of the reference FETs based on both 2-dimensional simulation and experimental results for the wavelength from 100 nm to 900 nm. The simulated the drain current of the nano-patterned FETs shows significantly higher value incident the reference FETs from ${\sim}1.7\;{\times}\;10^{-6}A$ to ${\sim}2.3\;{\times}\;10^{-6}A$ in the infrared range. The fabricated surface texturing of photo-transistors may be applied for high-efficiency photovoltaic devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.41-44
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• 2004

The trend of decreasing the minimal structure sizes in microelectronics is still being continued. Therefore in its roadmap the Semiconductor Industries Association predicts a printed minimum MOS-transistor channel length of 10 nm for the year 2018. Although the resolution of optical lithography still dramatically increases, there are known and proved solutions for structure sizes significantly below 50 nm up to now. In this work a new method for the fabrication of extremely small MOS-transistors with a channel length and width below 50 nm with low demands to the used lithography will be explained. It's a further development of our deposition and etchback technique which was used in earlier research to produce transistors with very small channel lengths down to 30 nm, with a scaling of the transistor's width. The used technique is proved in a first charge of MOS-transistors with a channel area of W=200 nm and L=80 nm. The full CMOS compatible technique is easily transferable to almost any other technology line and results in an excellent homogeneity and reproducibility of the generated structure size. The electrical characteristics of such small transistor will be analyzed and the ultimate limits of the technique will be discussed.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.22.1-22.1
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• 2009

차세대 CMOS 공정에서 유전상수가 높은 게이트 절연막과 함께 게이트 전극이 관심을 끌고 있다. 게이트 전극은 전도도가 높아야 하고 p-MOS, n-MOS에 맞는 일함수를 가져야 하며 열적 특성이 안정해야 한다. 탄탈룸 계열 탄화물이나 질화물은 게이트 전극으로 관심을 끌고 있는 물질이며 이를 원자층 화학증착법으로 박막화 하는 공정이 관심을 끌고 있다. 원자층 화학공정에서는 전구체의 역할이 중요하며 이의 기상반응 메카니즘, 표면 반응 메카니즘을 제대로 이해해야 한다. 본 연구에서는 TBTDET (tert-butylimido tris-diethylamido tantalum) 전구체의 반응 메커니즘을 FTIR(Fourier Transform Infrared)을 이용해 진단하였다. 또한 수소, 암모니아, 메탄을 이용한 열화학 원자층 증착, 플라즈마 원자층 증착 공정을 수행하여 박막을 얻고 이들의 특성을 평가하였다. 각 공정에 따라 반응 메커니즘이 달라지고 박막의 조성이 달라지며 또한 박막의 물성도 달라진다. 특히 박막에 형성되는 TaC, TaN, Ta3N5, Ta2O5 (증착 후 산소의 유입에 의해 형성됨) 등의 조성이 공정에 따라 달라지며 박막의 물성도 달라진다. 반응메카니즘의 연구를 통해 각 공정에서 어떠한 조성의 박막이 얻어지는 지를 규명하였고 박막의 밀도에 따라 산소유입량이 어떻게 달라지는 지를 규명하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.21-27
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• 2008

This paper describes a CMOS 16:1 binary-tree multiplexer(MUX) using $0.18-{\mu}m$ technology. To provide immunity for wide frequency range and process-and-temperature variations, the MUX adopts several delay compensation techniques. Simulation results show that the proposed MUX maintains the setup margins and hold margins close to the optimal value, i.e., 0.5UI, in wide frequency-range and in wide process-and-temperature variations, with standard deviation of 0.05UI approximately. These results represent that these proposed delay compensations are effective and the reliability is much improved although CMOS logic circuits are sensitive to those variations. The MUX is fabricated using $0.18-{\mu}m$ CMOS process, and tested with a test board. At power supply voltage of 1.8-V, maximum data-rate and area of the MUX is 1.65-Gb/s and 0.858 $mm^2$, respectively. The MUX dissipates a power of 24.12 mW, and output eye opening is 272.53 mV, 266.55 ps at 1.65-Gb/s operation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.252-258
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• 2013

In this paper, a thermally stable nickel silicide technology using the co-sputtering of nickel and titanium atoms capped with TiN layer is proposed for nano-scale metal oxide semiconductor field effect transistor (MOSFET) applications. The effects of the incorporation of titanium ingredient in the co-sputtered Ni layer are characterized as a function of Ti sputtering power. The difference between the one-step rapid thermal process (RTP) and two-step RTP for the silicidation process has also been studied. It is shown that a certain proportion of titanium incorporation with two-step RTP has the best thermal stability for this structure.