• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.40-45
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• 2008

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.3-4
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• 2006

본 논문에서는 nano-scale CMOSFET을 위해 Boron Cluster ($B_{18}H_{22}$)가 이온주입된 SOI 와 Bulk 기판들 이용하였으며 실리사이드의 열 안정성 개선을 위해 Ni-V을 증착한 것과 순수 Ni을 증착한 것을 비교 분석 하였다. 결과 SOI위에 Ni-V을 증착한 것이 제일 낮은 면 저항을 보여주었고 반대로 Bulk위에는 제일 높은 면 저항을 보여 주었다. 단면을 측정한 결과 SOI 위에 Ni-V을 증착한 동일 조건의 Ni보다 Silicide의 두께가 두껍게 형성된 것을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.24-25
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• 2006

In this study, Ni silicide on the SOI substrate doped B11 is proposed to improve thermal stability. The sheet resistance of Ni-silicide utilizing pure SOI substrate increased after the post-silicidation annealing at $600^{\circ}C$ for 30 min. However, using the proposed B11 implanted substrate, the sheet resistance showed stable characteristics after the post-silicidation annealing up to $700^{\circ}C$ for 30 min.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• Korean Journal of Materials Research
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• v.15 no.6
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• pp.426-430
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• 2005

Chemical mechanical polishing (CMP) is an essential process in the production of integrated circuits containing copper interconnects. The effect of alanine in reactive slurries representative of those that might be used in copper CMP was studied with the aim of improving selectivity between copper(Cu) film and tantalum-nitride(TaN) film. We investigated the pH effect of nano-colloidal silica slurry containing alanine through the chemical mechanical polishing test for the 8(inch) blanket wafers as deposited Cu and TaN film, respectively. The copper and tantalum-nitride removal rate decreased with the increase of pH and reaches the neutral at pH 7, then, with the further increase of pH to alkaline, the removal rate rise to increase soddenly. It was found that alkaline slurry has a higher removal rate than acidic and neutral slurries for copper film, but the removal rate of tantalum-nitride does not change much. These tests indicated that alanine may improve the CMP process by controlling the selectivity between Cu and TaN film.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.356-357
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• 2008

The effects of $O_2$ plasma ashing process for surface treatment of nano-wire Bio-FET were investigated. In order to evaluate the plasma damage introduced by $O_2$ plasma ashing, a back-gate biasing method was developed and the electrical characteristics as a function of $O_2$ plasma power were measured. Serious degradations of electrical characteristics of nano-wire Bio-FET were observed when the plasma power is higher than 50 W. For curing the plasma damages, a forming gas anneal (2 %, $H_2/N_2$) was carried out at $400^{\circ}C$. As a result, the electrical characteristics of nano-wire Bio-FET were considerably recovered.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.990-995
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• 2005

This paper reports the fabrication and characterization of $5\;\times\;5$ thermal cantilever array for nano-scaled memory device application. The $5\;\times\;5$ thermal cantilever array with integrated tip heater has been fabricated with MEMS technology on SOI wafer using 7 photo masking steps. All single-level cantilevers have a diode in order to eliminate any electrical cross-talk between adjacent tips. Electrical measurements of fabricated thermal cantilever away show its own thermal heating mechanism. Thermal heating is demonstrated by the reflow of coated photoresist on the cantilever array surface.