• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.26-38
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• 2015

고집적화를 위한 Floating Gate NAND 개발과정에서 몇 차례 기술적 한계상황에 직면하였었지만, Air-Gap, Double patterning, Multi-level Cell, Error Correction Code과 같은 breakthrough idea 을 활용하여 1Xnm까지 성공적인 scale-down 을 하였고 10nm 까지도 바라보고 있지만, 10nm 미만으로는 적절한 방안을 찾지 못한 상황입니다. CTD 의 3D NAND Flash는 Aspect Ratio, Poly channel의 intrinsic 특성, Data 보존 능력 등 해결 해야 할 issue 들이 남아 있지만, F.G Flash 의 지난 20년간 Lesson-learn 과 Band engineering, Channel Si, PUC 의 요소기술 개발 및 System algorithm 개발, QLC 개발 등을 통하여 F.G Flash를 넘어 지속적인 Cost-down 이 가능할 것입니다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.777-778
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• 2006

In this thesis, we design and implement a Flash Cache Core Module (FCCM) which operates on the YAFFS NAND flash memory. The FCCM applies memory replacement policy and prefetching policy based on the page reference pattern of applications. Also, implement the Clean-First memory replacement technique considering the characteristics of flash memory. In this method the decision is made according to page hit to apply prefetched waiting area. The FCCM decrease I/O hit frequency up to 37%, Compared with the linux cache and prefetching policy. Also, it operated using less memory for prefetching(maximum 24% and average 16%) compared with the linux kernel.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.138-142
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• 2019

As the NAND flash memory goes to 3D vertical Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure, the lateral charge migration can be critical in the reliability performance. Even more, with miniaturization of flash memory cell device, just a little movement of trapped charge can cause reliability problems. In this paper, we propose a method of predicting the trapped charge profile in the retention mode. Charge diffusivity in the charge trapping layer (Si₃N₄) was extracted experimentally, and the effect on the trapped charge profile was demonstrated by the simulation and experiment.

• Journal of IKEEE
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• v.28 no.1
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• pp.110-115
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• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.12
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• pp.1199-1203
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• 2010

Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.125-134
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• 2016

NAND flash memory has unique characteristics like as 'out-place-update' and limited lifetime compared with traditional storage systems. According to out-of-place update scheme, a number of invalid (or called dead) pages can be generated. In this case, garbage collection is needed to reclaim invalid pages. Because garbage collection results in not only erase operations but also copy operations of valid (or called live) pages to other blocks, many garbage collection techniques have proposed to reduce the overhead and to increase the lifetime of NAND Flash systems. This techniques sometimes select victim blocks including cold data for the wear leveling. However, most of them overlook the cost of selecting victim blocks including cold data. In this paper, we propose a garbage collection technique named CAPi (Cost Age with Proportion of invalid pages). Considering the additional overhead of what to select victim blocks including cold data, CAPi improves the response time in garbage collection and increase the lifetime in memory systems. Additionally, the proposed scheme also improves the efficiency of garbage collection by separating cold data from hot data in valid pages. In experimental evaluation, we showed that CAPi yields up to, at maximum, 73% improvement in lifetime compared with existing garbage collections.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Journal of the Korea Society of Computer and Information
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• v.20 no.12
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• pp.1-8
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• 2015

Wear leveling techniques have been studied to prolong the lifetime of NAND flash memory. Most of studies have used Program/Erase(P/E) cycles as wear index for wear leveling. Unfortunately, P/E cycles could not predict the real lifetime of NAND flash blocks. Therefore, these algorithms have the limited performance from prolonging the lifetime when applied to the SSD. In order to apply the real lifetime, wear leveling algorithms, which use raw Bit Error Rate(rBER) as wear index, have been studied in recent years. In this paper, we propose CrEWL(Cold data identification using raw Bit error rate in Wear Leveling), which uses rBER as wear index to apply to the real lifetime. The proposed wear leveling reduces an overhead of garbage collections by using HBSQ(Hot Block Sequence Queue) which identifies hot data. In order to reduce overhead of wear leveling, CrEWL does not perform wear leveling until rBER of the some blocks reaches a threshold value. We evaluate CrEWL in comparison with the previous studies under the traces having the different Hot/Cold rate, and the experimental results show that our wear leveling technique can reduce the overhead up to 41% and prolong the lifetime up to 72% compared with previous wear leveling techniques.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.21-31
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• 2010

Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.