• Transactions on Electrical and Electronic Materials
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• 제13권4호
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• 한국초전도ㆍ저온공학회논문지
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• 제5권1호
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• pp.123-127
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• 2003

For disseminating a ney IEC international standard of critical trmperature of NbTi,Nb$_3$Sn and Bi-2223 Composite Suterconductors, we develpted a measuring system and studied standardization of test method. The measuring system consisted of cryogenic reservoir, base plate, thermometer, voltmeter and current source. Various specimens of the Nbti, Nb$_3$Sn and Bi-2223 composite superconductors were tested using this system for measuring their critical temperatures. After measuring the resistance-temperature relation, the data were compensated with thermoelectric voltages for NbTi Nb$_3$Sn specimens. NbTi specimens showed 9.2 K ~ 9.5 K of transition temperature and Nb$_3$Sn specimen showed about 18 K. Bi-2223 specimens showed 104 K ~ 107 K of transition temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.29-30
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide ($SiO_2$) under both Negative-bias Temperature Instability(NBTI) and Hot-carrier-induced(HCI) stresses using P and NMOSFETs that are annealed with hydrogen or deuterium gas at high-pressure (1~5 atm.). Statistical parameter variations depend on the stress conditions. We suggest that deuterium bonds in $SiO_2$ film is effective in suppressing the generation of traps related to the energetic hot electrons.

• 한국산업정보학회논문지
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• 제19권4호
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• pp.33-39
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• 2014

본 논문에서는 나노미티 기술에서 HCI와 BTI와 같은 노화 현상에 의해 야기되는 MOSFET 디지털 회로의 실패를 정확히 예측을 위한 플립플롭 기반의 온-칩 노화 센싱 회로를 제안한다. 제안된 센싱 회로는 순차회로의 가드밴드 (guardband) 위반에 대한 경고를 나타내는 타이밍 윈도우를 이용해서 노화에 의한 회로의 동작 실패 전에 경고 비트를 발생한다. 발생된 비트는 고신뢰의 시스템 설계를 위한 적응형 셀프-튜닝 방법에서 제어 신호로 사용될 것이다. 노화 센싱 회로는 0.11um CMOS 기술을 사용해서 구현되었고, 파워-게이팅 구조를 가지는 $4{\times}4$ 곱셈기에 의해서 평가되었다.

• 한국전기전자재료학회논문지
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• 제21권8호
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• pp.687-694
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• 2008

This paper is focused on the improvement of MOS device reliability related to deuterium process. The injection of deuterium into the gate oxide film was achieved through two kind of method, high-pressure annealing and low-energy implantation at the back-end of line, for the purpose of the passivation of dangling bonds at $SiO_2/Si$ interface. Experimental results are presented for the degradation of 3-nm-thick gate oxide ($SiO_2$) under both negative-bias temperature instability (NBTI) and hot-carrier injection (HCI) stresses using P and NMOSFETs. Annealing process was rather difficult to control the concentration of deuterium. Because when the concentration of deuterium is redundant in gate oxide excess traps are generated and degrades the performance, we found annealing process did not show the improved characteristics in device reliability, compared to conventional process. However, deuterium ion implantation at the back-end process was effective method for the fabrication of the deuterated gate oxide. Device parameter variations under the electrical stresses depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to conventional process. Our result suggests the novel method to incorporate deuterium in the MOS structure for the reliability.

• World Technopolis Review
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• 제7권1호
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• pp.15-43
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• 2018

The lack of appropriate performance appraisal and evaluation of incubatees of technology incubation programmes in relation to entrepreneurship development in Nigeria is a major gap that needs to be bridged. This study examined the effect of selected technology incubation programme variables such as training, financing and marketing on entrepreneurship development in Nigeria. A closed-ended questionnaire was used for data collection from the quota-sampled population of the six (6) geo-political zones of Nigeria. Descriptive statistics were used to analyse the data while multiple regression was used to test the hypotheses. The results revealed that technology incubation training has a significant effect on entrepreneurial ability in Nigeria; there is a significant and positive effect of technology incubation financing on entrepreneurial funding portfolio; there is no significant impact of technology incubation marketing programme on entrepreneurial turnover; and technology incubation has no significant impact on entrepreneurial propensity. The study recommended that the National Board for Technology Incubation (NBTI) expand the training modules to capture pre, post and virtual incubatees; to facilitate access to risk funds, cheap capital and encourage establishment of venture capital; to improve on its marketing programme to encompass all marketing needs of incubatees beyond trade-fair participation. However, trade-fairs participation has a significant but limited effect on entrepreneurial turnover, while a technology incubation programme has no significant impact on entrepreneurial propensity, as only six (6) out of the twenty-nine (29) respondents started new venture from the incubation centers which are industrial training students and staff of the incubatees.

• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.996-1000
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• 2005

Experimental results are presented for the degradation of 3 nm-thick gate oxide $(SiO_2)$ under both Negative-bias Temperature Instability (NBTI) and Hot-carrier-induced (HCI) stresses using P and NMOSFETS, The devices are annealed with hydrogen or deuterium gas at high-pressure $(1\~5\;atm.)$ to introduce higher concentration in the gate oxide. Both interface trap and oxide bulk trap are found to dominate the reliability of gate oxide during electrical stress. The degradation mechanism depends on the condition of electrical stress that could change the location of damage area in the gate oxide. It was found the trap generation in the gate oxide film is mainly related to the breakage of Si-H bonds in the interface or the bulk area. We suggest that deuterium bonds in $SiO_2$ film are effective in suppressing the generation of traps related to the energetic hot carriers.

• Archives of Pharmacal Research
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• 제28권7호
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• pp.810-815
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• 2005

Previously, we have shown that astrocytes deprived of glucose became highly vulnerable to peroxynitrite, and adenosine and its metabolites attenuated the gliotoxicity via the preservation of cellular ATP level. Here, we found that adenosine and related metabolites prevented the disruption of mitochondrial transmembrane potential (MTP) in glucose-deprived rat primary astrocytes exposed to 3-morpholinosydnonimine (SIN-1), a peroxynitrite releasing agent. Exposure to glucose deprivation and SIN-1(2h) significantly disrupted MTP in astrocytes, and adenosine prevented it in dose-dependent manner with an $EC_{50}\;of\;5.08{\mu}M$. Adenosine also partially prevented the cell death by myxothiazol, a well-known inhibitor of mitochondrial respiration. Blockade of adenosine deamination or intracellular transport with erythro-9-(-hydroxy-3-nonyl)adenosine (EHNA) or S-(4-nitrobenzyl)-6-thioinosine (NBTI), respectively, completely reversed the protective effect of adenosine. Other purine nucleos(t)ides including inosine, guanosine, ATP, ADP, AMP, ITP, and GTP also showed similar protective effects. This study indicates that adenosine and related purine nucleos(t)ides may protect astrocytes from peroxynitrite-induced mitochondrial dysfunction.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.944-948
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• 2011

In this paper, flicker noise characteristic and channel hot carrier degradation of NMOSFETs with plasma nitrided oixde (PNO) and thermally nitrided oxide (TNO) are analyzed in depth. Compared with NMOSFET with TNO, flicker noise characteristic of NMOSFET with PNO is improved significantly because nitrogen density in PNO near the Si/$SiO_2$ interface is less than that in TNO. However, device degradation of NMOSFET with PNO by channel hot carrier stress is greater than that with TNO although PMOSFET with PNO showed greater immunity to NBTI degradation than that with TNO in previous study. Therefore, concurrent investigation of the reliability as well as low frequency noise characteristics of NMOSFET and PMOSFET is required for the development of high performance analog MOSFET technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.450-450
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• 2012

In recent days, advances in ZnO-based oxide semiconductor materials have accelerated the development of thin-film transistors (TFTs), which are the building blocks for active matrix flat-panel displays including liquid crystal displays (LCD) and organic light-emitting diodes (OLED). In particular, the development of high-mobility ZnO-based channel materials has been proven invaluable; thus, there have been many reports of high-performance TFTs with oxide semiconductor channels such as ZnO, InZnO (IZO), ZnSnO (ZTO), and InGaZnO (IGZO). The reliability of oxide TFTs can be improved by examining more stable oxide channel materials. In the present study, we investigated the effects of an ALD-deposited water vapor permeation barrier on the stability of ZnO and HfZnO (HZO) thin film transistors. The device without the water vapor barrier films showed a large turn-on voltage shift under negative bias temperature stress. On the other hand, the suitably protected device with the lowest water vapor transmission rate showed a dramatically improved device performance. As the value of the water vapor transmission rate of the barrier films was decreased, the turn-on voltage instability reduced. The results suggest that water vapor related traps are strongly related to the instability of ZnO and HfZnO TFTs and that a proper combination of water vapor permeation barriers plays an important role in suppressing the device instability.