• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.141-145
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• 2018

Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at $570^{\circ}C$ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above $500^{\circ}C$. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.

• 전자공학회논문지A
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• 제31A권12호
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1990년도 추계학술대회 논문집
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• pp.55-59
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• 1990

N-Channel polysilicon MOSFETs (W/L=20/1.5, 3, 5.10$\mu\textrm{m}$) were fabricated using RTP(Rapid Thermal Processor) and hydrogen passivation. The N+ Source, drain and gate were annealed and recrystallized using RTP at temperature of 1000$^{\circ}C$-1100$^{\circ}C$. But the active areas were now specially crystallized before growing the gate oxide. Without the hydrogen passivation, excellent transistor characteristics (ON/OFF=5${\times}$10$\^$6/, s=85mv/dec, I$\_$L/=51pA/$\mu\textrm{m}$) were obtained for 1.5$\mu\textrm{m}$ MOSFET. Also the transistor characteristics were improved by hydrogen passivation.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 마이크로전자및패키징학회지
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• 제30권2호
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• pp.43-51
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• 2023

본 논문에서는 전기차 전력변환 시스템의 근간이 되는 전력반도체 소자의 발전 방향과 차세대 전력반도체 소자인 wide bandgap (WBG)의 특징에 관해 소개하고자 한다. 현재까지의 주류인 Si insulated gate bipolar transistor (IGBT)의 특징에 관해 소개하고, 제조사 별 Si IGBT 개발 방향에 대해 다루었다. 또한 대표적인 WBG 전력반도체 소자인 SiC metal-oxide-semiconductor field-effect transistor (MOSFET)이 가지는 특징을 고찰하여 종래의 Si IGBT 소자 대비 SiC MOSFET이 가지는 효용 및 필요성에 대해 서술하였다. 또한 현 시점에서의 GaN 전력반도체 소자가 가지는 한계 및 그로 인해 전기자동차용 전력변환모듈 용으로 사용하기에 이슈인 점을 서술하였다.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1994년도 하계종합학술발표회 논문집
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• pp.404-408
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• 1994

• 한국통신학회:학술대회논문집
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• 한국통신학회 1992년도 하계종합학술발표회 논문집
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• pp.555-558
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• 1992

• 한국통신학회:학술대회논문집
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• 한국통신학회 1996년도 추계종합학술발표회 논문집
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• pp.1075-1078
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• 1996

• 한국통신학회:학술대회논문집
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• 한국통신학회 1992년도 추계종합학술발표회 논문집
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• pp.409-502
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• 1992

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.165-168
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• 2001

고 전계하에서 수직 및 수평 전계의 영향을 고려할 수 있는 Hewlett-Packard 이동도 모델을 구현하였다. HP 이동도 모델은 BANDIS에 구현되었다. 구현된 HP이동도 모델을 검증하기 위해 N-MOSFET과 P-MOSFET에 대해 모의실험을 수행하여 MEDICI와 비교한 결과, 드레인 전압-드레인 전류는 5% 이내의 최대 상대 오차를 보였고 전위 분포는 5% 이내의 최대 상대오차를 보였다. MEDICI에서는 1회 수렴을 하기위해 평균 4.6회 이하의 행렬 연산이 필요한 반면 BANDIS에서는 평균 4.3회 이하의 행렬 연산이 필요하다.